src/soc/simple/test/test_microwatt.py

   1 from openpower.simulator.program import Program
   2 from openpower.test.common import TestCase
   3
   4 import unittest
   5
   6 from nmigen import Module, Signal
   7 from nmigen.back.pysim import Simulator, Delay, Settle
   8 from nmutil.formaltest import FHDLTestCase
   9
  10 from soc.simple.issuer import TestIssuer
  11 from openpower.endian import bigendian
  12
  13
  14 from soc.config.test.test_loadstore import TestMemPspec
  15 from soc.simple.test.test_core import (setup_regs, check_regs,
  16                                        wait_for_busy_clear,
  17                                        wait_for_busy_hi)
  18 from soc.fu.compunits.test.test_compunit import (setup_test_memory,
  19                                                  check_sim_memory,
  20                                                  get_l0_mem)
  21
  22 from soc.simple.test.test_issuer import setup_i_memory
  23
  24 import sys
  25 sys.setrecursionlimit(10**6)
  26
  27
  28 class BinaryTestCase(FHDLTestCase):
  29     test_data = []
  30
  31     def __init__(self, name="general"):
  32         super().__init__(name)
  33         self.test_name = name
  34
  35     @unittest.skip("a bit big")
  36     def test_binary(self):
  37         with Program("1.bin", bigendian) as program:
  38             self.run_tst_program(program)
  39
  40     def test_binary(self):
  41         with Program("hello_world.bin", bigendian) as program:
  42             self.run_tst_program(program)
  43
  44     def run_tst_program(self, prog):
  45         initial_regs = [0] * 32
  46         tc = TestCase(prog, self.test_name, initial_regs, None, 0,
  47                       None, 0,
  48                       do_sim=False)
  49         self.test_data.append(tc)
  50
  51
  52 class TestRunner(FHDLTestCase):
  53     def __init__(self, tst_data):
  54         super().__init__("binary_runner")
  55         self.test_data = tst_data
  56
  57     def binary_runner(self):
  58         m = Module()
  59         comb = m.d.comb
  60         go_insn_i = Signal()
  61         pc_i = Signal(32)
  62         pc_i_ok = Signal()
  63
  64         pspec = TestMemPspec(ldst_ifacetype='test_bare_wb',
  65                              imem_ifacetype='test_bare_wb',
  66                              addr_wid=48,
  67                              mask_wid=8,
  68                              reg_wid=64,
  69                              imem_test_depth=32768,
  70                              dmem_test_depth=32768)
  71         m.submodules.issuer = issuer = TestIssuer(pspec)
  72         imem = issuer.imem._get_memory()
  73         core = issuer.core
  74         pdecode2 = core.pdecode2
  75         l0 = core.l0
  76
  77         comb += issuer.pc_i.data.eq(pc_i)
  78         comb += issuer.pc_i.ok.eq(pc_i_ok)
  79         comb += issuer.go_insn_i.eq(go_insn_i)
  80
  81         # nmigen Simulation
  82         sim = Simulator(m)
  83         sim.add_clock(1e-6)
  84
  85         def process():
  86
  87             for test in self.test_data:
  88
  89                 # get core going
  90                 yield core.bigendian_i.eq(bigendian)
  91                 yield core.core_start_i.eq(1)
  92                 yield
  93                 yield core.core_start_i.eq(0)
  94                 yield Settle()
  95
  96                 print(test.name)
  97                 program = test.program
  98                 self.subTest(test.name)
  99                 print("regs", test.regs)
 100                 print("sprs", test.sprs)
 101                 print("cr", test.cr)
 102                 print("mem", test.mem)
 103                 print("msr", test.msr)
 104                 print("assem", program.assembly)
 105                 instructions = list(program.generate_instructions())
 106
 107                 print("instructions", len(instructions))
 108
 109                 pc = 0  # start of memory
 110
 111                 yield from setup_i_memory(imem, pc, instructions)
 112                 # blech!  put the same listing into the data memory
 113                 data_mem = get_l0_mem(l0)
 114                 yield from setup_i_memory(data_mem, pc, instructions)
 115                 # yield from setup_test_memory(l0, sim)
 116                 yield from setup_regs(core, test)
 117
 118                 yield pc_i.eq(pc)
 119                 yield pc_i_ok.eq(1)
 120
 121                 while True:
 122
 123                     # start the instruction
 124                     yield go_insn_i.eq(1)
 125                     yield
 126                     yield pc_i_ok.eq(0)  # don't change PC from now on
 127                     yield go_insn_i.eq(0)      # and don't issue a new insn
 128                     yield from wait_for_busy_hi(core)
 129                     yield Settle()
 130
 131                     # wait until executed
 132                     ins = yield core.raw_opcode_i
 133                     pc = yield issuer.pc_o
 134                     print("instruction: 0x%x @ %x" % (ins & 0xffffffff, pc))
 135                     yield from wait_for_busy_clear(core)
 136
 137                     terminated = yield core.core_terminated_o
 138                     print("terminated", terminated)
 139
 140                     terminated = yield core.core_terminated_o
 141                     if terminated:
 142                         break
 143
 144             # register check
 145             # yield from check_regs(self, sim, core, test, code)
 146
 147             # Memory check
 148             # yield from check_sim_memory(self, l0, sim, code)
 149
 150         sim.add_sync_process(process)
 151         with sim.write_vcd("binary_issuer_simulator.vcd",
 152                            traces=[]):
 153             sim.run()
 154
 155
 156 if __name__ == "__main__":
 157     unittest.main(exit=False)
 158     suite = unittest.TestSuite()
 159     suite.addTest(TestRunner(BinaryTestCase.test_data))
 160
 161     runner = unittest.TextTestRunner()
 162     runner.run(suite)