src/soc/simple/test/test_microwatt.py

   1 from openpower.simulator.program import Program
   2 from openpower.test.common import TestCase
   3
   4 import unittest
   5
   6 from nmigen import Module, Signal
   7 from nmigen.back.pysim import Simulator, Delay, Settle
   8 from nmutil.formaltest import FHDLTestCase
   9
  10 from soc.simple.issuer import TestIssuer
  11 from openpower.endian import bigendian
  12
  13
  14 from soc.config.test.test_loadstore import TestMemPspec
  15 from soc.simple.test.test_core import (setup_regs, check_regs,
  16                                        wait_for_busy_clear,
  17                                        wait_for_busy_hi)
  18 from soc.fu.compunits.test.test_compunit import (check_sim_memory,
  19                                                  get_l0_mem)
  20
  21 from soc.simple.test.test_runner import setup_i_memory
  22
  23 import sys
  24 sys.setrecursionlimit(10**6)
  25
  26
  27 class BinaryTestCase(FHDLTestCase):
  28     test_data = []
  29
  30     def __init__(self, name="general"):
  31         super().__init__(name)
  32         self.test_name = name
  33
  34     @unittest.skip("a bit big")
  35     def test_binary(self):
  36         with Program("1.bin", bigendian) as program:
  37             self.run_tst_program(program)
  38
  39     def test_binary(self):
  40         with Program("hello_world.bin", bigendian) as program:
  41             self.run_tst_program(program)
  42
  43     def run_tst_program(self, prog):
  44         initial_regs = [0] * 32
  45         tc = TestCase(prog, self.test_name, initial_regs, None, 0,
  46                       None, 0,
  47                       do_sim=False)
  48         self.test_data.append(tc)
  49
  50
  51 class TestRunner(FHDLTestCase):
  52     def __init__(self, tst_data):
  53         super().__init__("binary_runner")
  54         self.test_data = tst_data
  55
  56     def binary_runner(self):
  57         m = Module()
  58         comb = m.d.comb
  59         go_insn_i = Signal()
  60         pc_i = Signal(32)
  61         pc_i_ok = Signal()
  62
  63         pspec = TestMemPspec(ldst_ifacetype='test_bare_wb',
  64                              imem_ifacetype='test_bare_wb',
  65                              addr_wid=48,
  66                              mask_wid=8,
  67                              reg_wid=64,
  68                              imem_test_depth=32768,
  69                              dmem_test_depth=32768)
  70         m.submodules.issuer = issuer = TestIssuer(pspec)
  71         imem = issuer.imem._get_memory()
  72         core = issuer.core
  73         pdecode2 = core.pdecode2
  74         l0 = core.l0
  75
  76         comb += issuer.pc_i.data.eq(pc_i)
  77         comb += issuer.pc_i.ok.eq(pc_i_ok)
  78         comb += issuer.go_insn_i.eq(go_insn_i)
  79
  80         # nmigen Simulation
  81         sim = Simulator(m)
  82         sim.add_clock(1e-6)
  83
  84         def process():
  85
  86             for test in self.test_data:
  87
  88                 # get core going
  89                 yield core.bigendian_i.eq(bigendian)
  90                 yield core.core_start_i.eq(1)
  91                 yield
  92                 yield core.core_start_i.eq(0)
  93                 yield Settle()
  94
  95                 print(test.name)
  96                 program = test.program
  97                 self.subTest(test.name)
  98                 print("regs", test.regs)
  99                 print("sprs", test.sprs)
 100                 print("cr", test.cr)
 101                 print("mem", test.mem)
 102                 print("msr", test.msr)
 103                 print("assem", program.assembly)
 104                 instructions = list(program.generate_instructions())
 105
 106                 print("instructions", len(instructions))
 107
 108                 pc = 0  # start of memory
 109
 110                 yield from setup_i_memory(imem, pc, instructions)
 111                 # blech!  put the same listing into the data memory
 112                 data_mem = get_l0_mem(l0)
 113                 yield from setup_i_memory(data_mem, pc, instructions)
 114                 yield from setup_regs(core, test)
 115
 116                 yield pc_i.eq(pc)
 117                 yield pc_i_ok.eq(1)
 118
 119                 while True:
 120
 121                     # start the instruction
 122                     yield go_insn_i.eq(1)
 123                     yield
 124                     yield pc_i_ok.eq(0)  # don't change PC from now on
 125                     yield go_insn_i.eq(0)      # and don't issue a new insn
 126                     yield from wait_for_busy_hi(core)
 127                     yield Settle()
 128
 129                     # wait until executed
 130                     ins = yield core.raw_opcode_i
 131                     pc = yield issuer.pc_o
 132                     print("instruction: 0x%x @ %x" % (ins & 0xffffffff, pc))
 133                     yield from wait_for_busy_clear(core)
 134
 135                     terminated = yield core.core_terminated_o
 136                     print("terminated", terminated)
 137
 138                     terminated = yield core.core_terminated_o
 139                     if terminated:
 140                         break
 141
 142             # register check
 143             # yield from check_regs(self, sim, core, test, code)
 144
 145             # Memory check
 146             # yield from check_sim_memory(self, l0, sim, code)
 147
 148         sim.add_sync_process(process)
 149         with sim.write_vcd("binary_issuer_simulator.vcd",
 150                            traces=[]):
 151             sim.run()
 152
 153
 154 if __name__ == "__main__":
 155     unittest.main(exit=False)
 156     suite = unittest.TestSuite()
 157     suite.addTest(TestRunner(BinaryTestCase.test_data))
 158
 159     runner = unittest.TextTestRunner()
 160     runner.run(suite)