src/soc/simple/test/test_runner.py

   1 """TestRunner class, runs TestIssuer instructions
   2
   3 related bugs:
   4
   5  * https://bugs.libre-soc.org/show_bug.cgi?id=363
   6 """
   7 from nmigen import Module, Signal, Cat, ClockSignal
   8 from nmigen.hdl.xfrm import ResetInserter
   9
  10 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
  11 # Also, check out the cxxsim nmigen branch, and latest yosys from git
  12 from nmutil.sim_tmp_alternative import Simulator, Settle
  13
  14 from nmutil.formaltest import FHDLTestCase
  15 from nmutil.gtkw import write_gtkw
  16 from nmigen.cli import rtlil
  17 from openpower.decoder.isa.caller import special_sprs, SVP64State
  18 from openpower.decoder.isa.all import ISA
  19 from openpower.endian import bigendian
  20
  21 from openpower.decoder.power_decoder import create_pdecode
  22 from openpower.decoder.power_decoder2 import PowerDecode2
  23 from soc.regfile.regfiles import StateRegs
  24
  25 from soc.simple.issuer import TestIssuerInternal
  26
  27 from soc.config.test.test_loadstore import TestMemPspec
  28 from soc.simple.test.test_core import (setup_regs, check_regs,
  29                                        wait_for_busy_clear,
  30                                        wait_for_busy_hi)
  31 from soc.fu.compunits.test.test_compunit import (setup_tst_memory,
  32                                                  check_sim_memory)
  33 from soc.debug.dmi import DBGCore, DBGCtrl, DBGStat
  34 from nmutil.util import wrap
  35 from soc.experiment.test.test_mmu_dcache import wb_get
  36
  37
  38 def setup_i_memory(imem, startaddr, instructions):
  39     mem = imem
  40     print("insn before, init mem", mem.depth, mem.width, mem,
  41           len(instructions))
  42     for i in range(mem.depth):
  43         yield mem._array[i].eq(0)
  44     yield Settle()
  45     startaddr //= 4  # instructions are 32-bit
  46     if mem.width == 32:
  47         mask = ((1 << 32)-1)
  48         for ins in instructions:
  49             if isinstance(ins, tuple):
  50                 insn, code = ins
  51             else:
  52                 insn, code = ins, ''
  53             insn = insn & 0xffffffff
  54             yield mem._array[startaddr].eq(insn)
  55             yield Settle()
  56             if insn != 0:
  57                 print("instr: %06x 0x%x %s" % (4*startaddr, insn, code))
  58             startaddr += 1
  59             startaddr = startaddr & mask
  60         return
  61
  62     # 64 bit
  63     mask = ((1 << 64)-1)
  64     for ins in instructions:
  65         if isinstance(ins, tuple):
  66             insn, code = ins
  67         else:
  68             insn, code = ins, ''
  69         insn = insn & 0xffffffff
  70         msbs = (startaddr >> 1) & mask
  71         val = yield mem._array[msbs]
  72         if insn != 0:
  73             print("before set", hex(4*startaddr),
  74                   hex(msbs), hex(val), hex(insn))
  75         lsb = 1 if (startaddr & 1) else 0
  76         val = (val | (insn << (lsb*32)))
  77         val = val & mask
  78         yield mem._array[msbs].eq(val)
  79         yield Settle()
  80         if insn != 0:
  81             print("after  set", hex(4*startaddr), hex(msbs), hex(val))
  82             print("instr: %06x 0x%x %s %08x" % (4*startaddr, insn, code, val))
  83         startaddr += 1
  84         startaddr = startaddr & mask
  85
  86
  87 def set_dmi(dmi, addr, data):
  88     yield dmi.req_i.eq(1)
  89     yield dmi.addr_i.eq(addr)
  90     yield dmi.din.eq(data)
  91     yield dmi.we_i.eq(1)
  92     while True:
  93         ack = yield dmi.ack_o
  94         if ack:
  95             break
  96         yield
  97     yield
  98     yield dmi.req_i.eq(0)
  99     yield dmi.addr_i.eq(0)
 100     yield dmi.din.eq(0)
 101     yield dmi.we_i.eq(0)
 102     yield
 103
 104
 105 def get_dmi(dmi, addr):
 106     yield dmi.req_i.eq(1)
 107     yield dmi.addr_i.eq(addr)
 108     yield dmi.din.eq(0)
 109     yield dmi.we_i.eq(0)
 110     while True:
 111         ack = yield dmi.ack_o
 112         if ack:
 113             break
 114         yield
 115     yield  # wait one
 116     data = yield dmi.dout  # get data after ack valid for 1 cycle
 117     yield dmi.req_i.eq(0)
 118     yield dmi.addr_i.eq(0)
 119     yield dmi.we_i.eq(0)
 120     yield
 121     return data
 122
 123
 124 class TestRunner(FHDLTestCase):
 125     def __init__(self, tst_data, microwatt_mmu=False, rom=None,
 126                         svp64=True):
 127         super().__init__("run_all")
 128         self.test_data = tst_data
 129         self.microwatt_mmu = microwatt_mmu
 130         self.rom = rom
 131         self.svp64 = svp64
 132
 133     def run_all(self):
 134         m = Module()
 135         comb = m.d.comb
 136         pc_i = Signal(32)
 137         svstate_i = Signal(64)
 138
 139         if self.microwatt_mmu:
 140             ldst_ifacetype = 'test_mmu_cache_wb'
 141         else:
 142             ldst_ifacetype = 'test_bare_wb'
 143         imem_ifacetype = 'test_bare_wb'
 144
 145         pspec = TestMemPspec(ldst_ifacetype=ldst_ifacetype,
 146                              imem_ifacetype=imem_ifacetype,
 147                              addr_wid=48,
 148                              mask_wid=8,
 149                              imem_reg_wid=64,
 150                              # wb_data_width=32,
 151                              use_pll=False,
 152                              nocore=False,
 153                              xics=False,
 154                              gpio=False,
 155                              regreduce=True,
 156                              svp64=self.svp64,
 157                              mmu=self.microwatt_mmu,
 158                              reg_wid=64)
 159         #hard_reset = Signal(reset_less=True)
 160         issuer = TestIssuerInternal(pspec)
 161         # use DMI RESET command instead, this does actually work though
 162         #issuer = ResetInserter({'coresync': hard_reset,
 163         #                        'sync': hard_reset})(issuer)
 164         m.submodules.issuer = issuer
 165         imem = issuer.imem._get_memory()
 166         core = issuer.core
 167         dmi = issuer.dbg.dmi
 168         pdecode2 = issuer.pdecode2
 169         l0 = core.l0
 170         regreduce_en = pspec.regreduce_en == True
 171
 172         #simdec = create_pdecode()
 173         simdec2 = PowerDecode2(None, regreduce_en=regreduce_en)
 174         m.submodules.simdec2 = simdec2  # pain in the neck
 175
 176         # run core clock at same rate as test clock
 177         intclk = ClockSignal("coresync")
 178         comb += intclk.eq(ClockSignal())
 179
 180         comb += issuer.pc_i.data.eq(pc_i)
 181         comb += issuer.svstate_i.data.eq(svstate_i)
 182
 183         # nmigen Simulation
 184         sim = Simulator(m)
 185         sim.add_clock(1e-6)
 186
 187         def process():
 188
 189             # start in stopped
 190             yield from set_dmi(dmi, DBGCore.CTRL, 1<<DBGCtrl.STOP)
 191             yield
 192
 193             # get each test, completely reset the core, and run it
 194
 195             for test in self.test_data:
 196
 197                 # set up bigendian (TODO: don't do this, use MSR)
 198                 yield issuer.core_bigendian_i.eq(bigendian)
 199                 yield Settle()
 200
 201                 yield
 202                 yield
 203                 yield
 204                 yield
 205
 206                 print(test.name)
 207                 program = test.program
 208                 with self.subTest(test.name):
 209                     print("regs", test.regs)
 210                     print("sprs", test.sprs)
 211                     print("cr", test.cr)
 212                     print("mem", test.mem)
 213                     print("msr", test.msr)
 214                     print("assem", program.assembly)
 215                     gen = list(program.generate_instructions())
 216                     insncode = program.assembly.splitlines()
 217                     instructions = list(zip(gen, insncode))
 218
 219                     # set up the Simulator (which must track TestIssuer exactly)
 220                     sim = ISA(simdec2, test.regs, test.sprs, test.cr, test.mem,
 221                               test.msr,
 222                               initial_insns=gen, respect_pc=True,
 223                               disassembly=insncode,
 224                               bigendian=bigendian,
 225                               initial_svstate=test.svstate)
 226
 227                     # establish the TestIssuer context (mem, regs etc)
 228
 229                     pc = 0  # start address
 230                     counter = 0  # test to pause/start
 231
 232                     yield from setup_i_memory(imem, pc, instructions)
 233                     yield from setup_tst_memory(l0, sim)
 234                     yield from setup_regs(pdecode2, core, test)
 235
 236                     # set PC and SVSTATE
 237                     yield pc_i.eq(pc)
 238                     yield issuer.pc_i.ok.eq(1)
 239
 240                     initial_svstate = test.svstate
 241                     if isinstance(initial_svstate, int):
 242                         initial_svstate = SVP64State(initial_svstate)
 243                     yield svstate_i.eq(initial_svstate.value)
 244                     yield issuer.svstate_i.ok.eq(1)
 245                     yield
 246
 247                     print("instructions", instructions)
 248
 249                     # run the loop of the instructions on the current test
 250                     index = sim.pc.CIA.value//4
 251                     while index < len(instructions):
 252                         ins, code = instructions[index]
 253
 254                         print("instruction: 0x{:X}".format(ins & 0xffffffff))
 255                         print(index, code)
 256
 257                         if counter == 0:
 258                             # start the core
 259                             yield
 260                             yield from set_dmi(dmi, DBGCore.CTRL,
 261                                                1<<DBGCtrl.START)
 262                             yield issuer.pc_i.ok.eq(0) # no change PC after this
 263                             yield issuer.svstate_i.ok.eq(0) # ditto
 264                             yield
 265                             yield
 266
 267                         counter = counter + 1
 268
 269                         # wait until executed
 270                         while not (yield issuer.insn_done):
 271                             yield
 272
 273                         # set up simulated instruction (in simdec2)
 274                         try:
 275                             yield from sim.setup_one()
 276                         except KeyError:  # instruction not in imem: stop
 277                             break
 278                         yield Settle()
 279
 280                         # call simulated operation
 281                         print("sim", code)
 282                         yield from sim.execute_one()
 283                         yield Settle()
 284                         index = sim.pc.CIA.value//4
 285
 286                         terminated = yield issuer.dbg.terminated_o
 287                         print("terminated", terminated)
 288
 289                         if index >= len(instructions):
 290                             print ("index over, send dmi stop")
 291                             # stop at end
 292                             yield from set_dmi(dmi, DBGCore.CTRL,
 293                                                1<<DBGCtrl.STOP)
 294                             yield
 295                             yield
 296
 297                         # register check
 298                         yield from check_regs(self, sim, core, test, code)
 299
 300                         # Memory check
 301                         yield from check_sim_memory(self, l0, sim, code)
 302
 303                         terminated = yield issuer.dbg.terminated_o
 304                         print("terminated(2)", terminated)
 305                         if terminated:
 306                             break
 307
 308                 # stop at end
 309                 yield from set_dmi(dmi, DBGCore.CTRL, 1<<DBGCtrl.STOP)
 310                 yield
 311                 yield
 312
 313                 # get CR
 314                 cr = yield from get_dmi(dmi, DBGCore.CR)
 315                 print("after test %s cr value %x" % (test.name, cr))
 316
 317                 # get XER
 318                 xer = yield from get_dmi(dmi, DBGCore.XER)
 319                 print("after test %s XER value %x" % (test.name, xer))
 320
 321                 # test of dmi reg get
 322                 for int_reg in range(32):
 323                     yield from set_dmi(dmi, DBGCore.GSPR_IDX, int_reg)
 324                     value = yield from get_dmi(dmi, DBGCore.GSPR_DATA)
 325
 326                     print("after test %s reg %2d value %x" %
 327                           (test.name, int_reg, value))
 328
 329                 # pull a reset
 330                 yield from set_dmi(dmi, DBGCore.CTRL, 1<<DBGCtrl.RESET)
 331                 yield
 332
 333         styles = {
 334             'dec': {'base': 'dec'},
 335             'bin': {'base': 'bin'},
 336             'closed': {'closed': True}
 337         }
 338
 339         traces = [
 340             'clk',
 341             ('state machines', 'closed', [
 342                 'fetch_pc_valid_i', 'fetch_pc_ready_o',
 343                 'fetch_fsm_state',
 344                 'fetch_insn_valid_o', 'fetch_insn_ready_i',
 345                 'pred_insn_valid_i', 'pred_insn_ready_o',
 346                 'fetch_predicate_state',
 347                 'pred_mask_valid_o', 'pred_mask_ready_i',
 348                 'issue_fsm_state',
 349                 'exec_insn_valid_i', 'exec_insn_ready_o',
 350                 'exec_fsm_state',
 351                 'exec_pc_valid_o', 'exec_pc_ready_i',
 352                 'insn_done', 'core_stop_o', 'pc_i_ok', 'pc_changed',
 353                 'is_last', 'dec2.no_out_vec']),
 354             {'comment': 'fetch and decode'},
 355             (None, 'dec', [
 356                 'cia[63:0]', 'nia[63:0]', 'pc[63:0]',
 357                 'cur_pc[63:0]', 'core_core_cia[63:0]']),
 358             'raw_insn_i[31:0]',
 359             'raw_opcode_in[31:0]', 'insn_type',
 360             ('svp64 decoding', 'closed', [
 361                 'svp64_rm[23:0]', ('dec2.extra[8:0]', 'bin'),
 362                 'dec2.sv_rm_dec.mode', 'dec2.sv_rm_dec.predmode',
 363                 'dec2.sv_rm_dec.ptype_in',
 364                 'dec2.sv_rm_dec.dstpred[2:0]', 'dec2.sv_rm_dec.srcpred[2:0]',
 365                 'dstmask[63:0]', 'srcmask[63:0]',
 366                 'dregread[4:0]', 'dinvert',
 367                 'sregread[4:0]', 'sinvert',
 368                 'core.int.pred__addr[4:0]', 'core.int.pred__data_o[63:0]',
 369                 'core.int.pred__ren']),
 370             ('register augmentation', 'dec', 'closed', [
 371                 {'comment': 'v3.0b registers'},
 372                 'dec2.dec_o.RT[4:0]',
 373                 'dec2.dec_a.RA[4:0]',
 374                 'dec2.dec_b.RB[4:0]',
 375                 ('Rdest', [
 376                     'dec2.o_svdec.reg_in[4:0]',
 377                     ('dec2.o_svdec.spec[2:0]', 'bin'),
 378                     'dec2.o_svdec.reg_out[6:0]']),
 379                 ('Rsrc1', [
 380                     'dec2.in1_svdec.reg_in[4:0]',
 381                     ('dec2.in1_svdec.spec[2:0]', 'bin'),
 382                     'dec2.in1_svdec.reg_out[6:0]']),
 383                 ('Rsrc1', [
 384                     'dec2.in2_svdec.reg_in[4:0]',
 385                     ('dec2.in2_svdec.spec[2:0]', 'bin'),
 386                     'dec2.in2_svdec.reg_out[6:0]']),
 387                 {'comment': 'SVP64 registers'},
 388                 'dec2.rego[6:0]', 'dec2.reg1[6:0]', 'dec2.reg2[6:0]'
 389             ]),
 390             {'comment': 'svp64 context'},
 391             'core_core_vl[6:0]', 'core_core_maxvl[6:0]',
 392             'core_core_srcstep[6:0]', 'next_srcstep[6:0]',
 393             'core_core_dststep[6:0]',
 394             {'comment': 'issue and execute'},
 395             'core.core_core_insn_type',
 396             (None, 'dec', [
 397                 'core_rego[6:0]', 'core_reg1[6:0]', 'core_reg2[6:0]']),
 398             'issue_i', 'busy_o',
 399             {'comment': 'dmi'},
 400             'dbg.dmi_req_i', 'dbg.dmi_ack_o',
 401             {'comment': 'instruction memory'},
 402             'imem.sram.rdport.memory(0)[63:0]',
 403             {'comment': 'registers'},
 404             # match with soc.regfile.regfiles.IntRegs port names
 405             'core.int.rp_src1.memory(0)[63:0]',
 406             'core.int.rp_src1.memory(1)[63:0]',
 407             'core.int.rp_src1.memory(2)[63:0]',
 408             'core.int.rp_src1.memory(3)[63:0]',
 409             'core.int.rp_src1.memory(4)[63:0]',
 410             'core.int.rp_src1.memory(5)[63:0]',
 411             'core.int.rp_src1.memory(6)[63:0]',
 412             'core.int.rp_src1.memory(7)[63:0]',
 413             'core.int.rp_src1.memory(9)[63:0]',
 414             'core.int.rp_src1.memory(10)[63:0]',
 415             'core.int.rp_src1.memory(13)[63:0]',
 416             {'comment': 'memory port interface'},
 417             'core.l0.pimem.ldst_port0_is_ld_i',
 418             'core.l0.pimem.ldst_port0_is_st_i',
 419             'core.l0.pimem.ldst_port0_busy_o',
 420             'core.l0.pimem.ldst_port0_addr_i[47:0]',
 421             'core.l0.pimem.ldst_port0_addr_i_ok',
 422             'core.l0.pimem.ldst_port0_addr_ok_o',
 423             'core.l0.pimem.ldst_port0_st_data_i[63:0]',
 424             'core.l0.pimem.ldst_port0_st_data_i_ok',
 425             'core.l0.pimem.ldst_port0_ld_data_o[63:0]',
 426             'core.l0.pimem.ldst_port0_ld_data_o_ok'
 427         ]
 428
 429         if self.microwatt_mmu:
 430             traces += [
 431                 {'comment': 'microwatt_mmu'},
 432                 'core.fus.mmu0.alu_mmu0.illegal',
 433                 'core.fus.mmu0.alu_mmu0.debug0[3:0]',
 434                 'core.fus.mmu0.alu_mmu0.mmu.state',
 435                 'core.fus.mmu0.alu_mmu0.mmu.pid[31:0]',
 436                 'core.fus.mmu0.alu_mmu0.mmu.prtbl[63:0]',
 437                 {'comment': 'wishbone_memory'},
 438                 'core.fus.mmu0.alu_mmu0.dcache.stb',
 439                 'core.fus.mmu0.alu_mmu0.dcache.cyc',
 440                 'core.fus.mmu0.alu_mmu0.dcache.we',
 441                 'core.fus.mmu0.alu_mmu0.dcache.ack',
 442                 'core.fus.mmu0.alu_mmu0.dcache.stall,'
 443             ]
 444
 445         write_gtkw("issuer_simulator.gtkw",
 446                    "issuer_simulator.vcd",
 447                    traces, styles, module='top.issuer')
 448
 449         # add run of instructions
 450         sim.add_sync_process(process)
 451
 452         # optionally, if a wishbone-based ROM is passed in, run that as an
 453         # extra emulated process
 454         if self.rom is not None:
 455             dcache = core.fus.fus["mmu0"].alu.dcache
 456             default_mem = self.rom
 457             sim.add_sync_process(wrap(wb_get(dcache, default_mem, "DCACHE")))
 458
 459         with sim.write_vcd("issuer_simulator.vcd"):
 460             sim.run()