src/soc/simulator/test_div_sim.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 import unittest
   5 from soc.decoder.power_decoder import (create_pdecode)
   6 from soc.decoder.power_enums import (Function, MicrOp,
   7                                      In1Sel, In2Sel, In3Sel,
   8                                      OutSel, RC, LdstLen, CryIn,
   9                                      single_bit_flags, Form, SPR,
  10                                      get_signal_name, get_csv)
  11 from soc.decoder.power_decoder2 import (PowerDecode2)
  12 from soc.simulator.program import Program
  13 from soc.simulator.qemu import run_program
  14 from soc.decoder.isa.all import ISA
  15 from soc.fu.test.common import TestCase
  16 from soc.simulator.test_sim import DecoderBase
  17
  18
  19
  20 class DivTestCases(FHDLTestCase):
  21     test_data = []
  22
  23     def __init__(self, name="div"):
  24         super().__init__(name)
  25         self.test_name = name
  26
  27     def test_0_divw(self):
  28         lst = ["addi 1, 0, 0x5678",
  29                "addi 2, 0, 0x1234",
  30                "divw  3, 1, 2",
  31                ]
  32         with Program(lst) as program:
  33             self.run_tst_program(program, [1, 2, 3])
  34
  35     def test_1_divw_(self):
  36         lst = ["addi 1, 0, 0x5678",
  37                "addi 2, 0, 0x1234",
  38                "divw.  3, 1, 2",
  39                ]
  40         with Program(lst) as program:
  41             self.run_tst_program(program, [1, 2, 3])
  42
  43     def test_2_divw_(self):
  44         lst = ["addi 1, 0, 0x1234",
  45                "addi 2, 0, 0x5678",
  46                "divw.  3, 1, 2",
  47                ]
  48         with Program(lst) as program:
  49             self.run_tst_program(program, [1, 2, 3])
  50
  51     def test_1_divwe(self):
  52         lst = ["addi 1, 0, 0x5678",
  53                "addi 2, 0, 0x1234",
  54                "divwe  3, 1, 2",
  55                ]
  56         with Program(lst) as program:
  57             self.run_tst_program(program, [1, 2, 3])
  58
  59     def test_2_divweu(self):
  60         lst = ["addi 1, 0, 0x5678",
  61                "addi 2, 0, 0x1234",
  62                "divweu  3, 1, 2",
  63                ]
  64         with Program(lst) as program:
  65             self.run_tst_program(program, [1, 2, 3])
  66
  67     def test_4_moduw(self):
  68         lst = ["addi 1, 0, 0x5678",
  69                "addi 2, 0, 0x1234",
  70                "moduw  3, 1, 2",
  71                ]
  72         with Program(lst) as program:
  73             self.run_tst_program(program, [1, 2, 3])
  74
  75     def test_5_div_regression(self):
  76         lst = ["addi 1, 0, 0x4",
  77                "addi 2, 0, 0x2",
  78                "neg 2, 2",
  79                "neg 1, 1",
  80                "divwo  3, 1, 2",
  81                ]
  82         with Program(lst) as program:
  83             self.run_tst_program(program, [1, 2, 3])
  84
  85     def run_tst_program(self, prog, initial_regs=None, initial_sprs=None,
  86                                     initial_mem=None):
  87         initial_regs = [0] * 32
  88         tc = TestCase(prog, self.test_name, initial_regs, initial_sprs, 0,
  89                                             initial_mem, 0)
  90         self.test_data.append(tc)
  91
  92
  93 class DivZeroTestCases(FHDLTestCase):
  94     test_data = []
  95
  96     def __init__(self, name="divbyzero"):
  97         super().__init__(name)
  98         self.test_name = name
  99
 100     def test_0_divw(self):
 101         lst = ["addi 1, 0, 0x5678",
 102                "addi 2, 0, 0x0",
 103                "divw  3, 1, 2",
 104                ]
 105         with Program(lst) as program:
 106             self.run_tst_program(program, [1, 2, 3])
 107
 108     def test_1_divwe(self):
 109         lst = ["addi 1, 0, 0x5678",
 110                "addi 2, 0, 0x0",
 111                "divwe  3, 1, 2",
 112                ]
 113         with Program(lst) as program:
 114             self.run_tst_program(program, [1, 2, 3])
 115
 116     def test_2_divweu(self):
 117         lst = ["addi 1, 0, 0x5678",
 118                "addi 2, 0, 0x0",
 119                "divweu  3, 1, 2",
 120                ]
 121         with Program(lst) as program:
 122             self.run_tst_program(program, [1, 2, 3])
 123
 124     def test_4_moduw(self):
 125         lst = ["addi 1, 0, 0x5678",
 126                "addi 2, 0, 0x0",
 127                "moduw  3, 1, 2",
 128                ]
 129         with Program(lst) as program:
 130             self.run_tst_program(program, [1, 2, 3])
 131
 132     def run_tst_program(self, prog, initial_regs=None, initial_sprs=None,
 133                                     initial_mem=None):
 134         initial_regs = [0] * 32
 135         tc = TestCase(prog, self.test_name, initial_regs, initial_sprs, 0,
 136                                             initial_mem, 0)
 137         self.test_data.append(tc)
 138
 139
 140
 141 class DivDecoderTestCase(DecoderBase, DivTestCases):
 142     pass
 143
 144 class DivZeroDecoderTestCase(DecoderBase, DivZeroTestCases):
 145     pass
 146
 147 if __name__ == "__main__":
 148     unittest.main()