src/soc/simulator/test_div_sim.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmigen.test.utils import FHDLTestCase
   4 import unittest
   5 from soc.decoder.power_decoder import (create_pdecode)
   6 from soc.decoder.power_enums import (Function, InternalOp,
   7                                      In1Sel, In2Sel, In3Sel,
   8                                      OutSel, RC, LdstLen, CryIn,
   9                                      single_bit_flags, Form, SPR,
  10                                      get_signal_name, get_csv)
  11 from soc.decoder.power_decoder2 import (PowerDecode2)
  12 from soc.simulator.program import Program
  13 from soc.simulator.qemu import run_program
  14 from soc.decoder.isa.all import ISA
  15 from soc.fu.test.common import TestCase
  16 from soc.simulator.test_sim import DecoderBase
  17
  18
  19
  20 class DivTestCases(FHDLTestCase):
  21     test_data = []
  22
  23     def __init__(self, name="general"):
  24         super().__init__(name)
  25         self.test_name = name
  26
  27     def test_0_divw(self):
  28         lst = ["addi 1, 0, 0x5678",
  29                "addi 2, 0, 0x1234",
  30                "divw  3, 1, 2",
  31                ]
  32         with Program(lst) as program:
  33             self.run_tst_program(program, [1, 2, 3])
  34
  35     def test_1_divw_byzero(self):
  36         lst = ["addi 1, 0, 0x5678",
  37                "addi 2, 0, 0x0",
  38                "divw  3, 1, 2",
  39                ]
  40         with Program(lst) as program:
  41             self.run_tst_program(program, [1, 2, 3])
  42
  43     def test_2_moduw(self):
  44         lst = ["addi 1, 0, 0x5678",
  45                "addi 2, 0, 0x1234",
  46                "moduw  3, 1, 2",
  47                ]
  48         with Program(lst) as program:
  49             self.run_tst_program(program, [1, 2, 3])
  50
  51     def run_tst_program(self, prog, initial_regs=None, initial_sprs=None,
  52                                     initial_mem=None):
  53         initial_regs = [0] * 32
  54         tc = TestCase(prog, self.test_name, initial_regs, initial_sprs, 0,
  55                                             initial_mem, 0)
  56         self.test_data.append(tc)
  57
  58
  59 class DecoderTestCase(DecoderBase, DivTestCases):
  60     pass
  61
  62
  63 if __name__ == "__main__":
  64     unittest.main()