4926cb112e7be655bd314465bf5c0cec8107218e
[soc.git] / src / soc / sv / svp64.py
1 # SPDX-License-Identifier: LGPLv3+
2 # Copyright (C) 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Funded by NLnet http://nlnet.nl
4 """SVP64 RM (Remap) Record.
5
6 https://libre-soc.org/openpower/sv/svp64/
7
8 | Field Name | Field bits | Description |
9 |------------|------------|----------------------------------------|
10 | MASKMODE | `0` | Execution (predication) Mask Kind |
11 | MASK | `1:3` | Execution Mask |
12 | ELWIDTH | `4:5` | Element Width |
13 | ELWIDTH_SRC | `6:7` | Element Width for Source |
14 | SUBVL | `8:9` | Sub-vector length |
15 | EXTRA | `10:18` | context-dependent extra |
16 | MODE | `19:23` | changes Vector behaviour |
17 """
18
19 from nmigen import Record
20
21 class SVP64Rec(Record):
22 def __init__(self, name=None):
23 Record.__init__(self, layout=[("mmode" , 1),
24 ("mask" , 3),
25 ("elwidth" , 2),
26 ("ewsrc" , 2),
27 ("extra" , 9),
28 ("mode" , 5)], name=name)
29
30 def ports(self):
31 return [self.mmode, self.mask, self.elwidth, self.ewsrc,
32 self.extra, self.mode]
33