0a9af5a6c65386def55e9b68f2a204ef7c868a3d
[soc.git] / src / soc / sv / trans / svp64.py
1 # SPDX-License-Identifier: LGPLv3+
2 # Copyright (C) 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Funded by NLnet http://nlnet.nl
4
5 """SVP64 OpenPOWER v3.0B assembly translator
6
7 This class takes raw svp64 assembly mnemonics (aliases excluded) and
8 creates an EXT001-encoded "svp64 prefix" followed by a v3.0B opcode.
9
10 It is very simple and straightforward, the only weirdness being the
11 extraction of the register information and conversion to v3.0B numbering.
12
13 Encoding format of svp64: https://libre-soc.org/openpower/sv/svp64/
14 Bugtracker: https://bugs.libre-soc.org/show_bug.cgi?id=578
15 """
16
17 import os, sys
18 from collections import OrderedDict
19
20 from soc.decoder.pseudo.pagereader import ISA
21 from soc.decoder.power_enums import get_csv, find_wiki_dir
22
23
24 # identifies register by type
25 def is_CR_3bit(regname):
26 return regname in ['BF', 'BFA']
27
28 def is_CR_5bit(regname):
29 return regname in ['BA', 'BB', 'BC', 'BI', 'BT']
30
31 def is_GPR(regname):
32 return regname in ['RA', 'RB', 'RC', 'RS', 'RT']
33
34 def get_regtype(regname):
35 if is_CR_3bit(regname):
36 return "CR_3bit"
37 if is_CR_5bit(regname):
38 return "CR_5bit"
39 if is_GPR(regname):
40 return "GPR"
41
42 # decode GPR into sv extra
43 def get_extra_gpr(etype, regmode, field):
44 if regmode == 'scalar':
45 # cut into 2-bits 5-bits SS FFFFF
46 sv_extra = field >> 5
47 field = field & 0b11111
48 else:
49 # cut into 5-bits 2-bits FFFFF SS
50 sv_extra = field & 0b11
51 field = field >> 2
52 return sv_extra, field
53
54
55 # decode 3-bit CR into sv extra
56 def get_extra_cr_3bit(etype, regmode, field):
57 if regmode == 'scalar':
58 # cut into 2-bits 3-bits SS FFF
59 sv_extra = field >> 3
60 field = field & 0b111
61 else:
62 # cut into 3-bits 4-bits FFF SSSS but will cut 2 zeros off later
63 sv_extra = field & 0b1111
64 field = field >> 4
65 return sv_extra, field
66
67
68 # decodes SUBVL
69 def decode_subvl(encoding):
70 pmap = {'2': 0b01, '3': 0b10, '4': 0b11}
71 assert encoding in pmap, \
72 "encoding %s for SUBVL not recognised" % encoding
73 return pmap[encoding]
74
75
76 # decodes elwidth
77 def decode_elwidth(encoding):
78 pmap = {'8': 0b11, '16': 0b10, '32': 0b01}
79 assert encoding in pmap, \
80 "encoding %s for elwidth not recognised" % encoding
81 return pmap[encoding]
82
83
84 # decodes predicate register encoding
85 def decode_predicate(encoding):
86 pmap = { # integer
87 '1<<r3': (0, 0b001),
88 'r3' : (0, 0b010),
89 '~r3' : (0, 0b011),
90 'r10' : (0, 0b100),
91 '~r10' : (0, 0b101),
92 'r30' : (0, 0b110),
93 '~r30' : (0, 0b111),
94 # CR
95 'lt' : (1, 0b000),
96 'nl' : (1, 0b001), 'ge' : (1, 0b001), # same value
97 'gt' : (1, 0b010),
98 'ng' : (1, 0b011), 'le' : (1, 0b011), # same value
99 'eq' : (1, 0b100),
100 'ne' : (1, 0b101),
101 'so' : (1, 0b110), 'un' : (1, 0b110), # same value
102 'ns' : (1, 0b111), 'nu' : (1, 0b111), # same value
103 }
104 assert encoding in pmap, \
105 "encoding %s for predicate not recognised" % encoding
106 return pmap[encoding]
107
108
109 # decodes "Mode" in similar way to BO field (supposed to, anyway)
110 def decode_bo(encoding):
111 pmap = { # TODO: double-check that these are the same as Branch BO
112 'lt' : 0b000,
113 'nl' : 0b001, 'ge' : 0b001, # same value
114 'gt' : 0b010,
115 'ng' : 0b011, 'le' : 0b011, # same value
116 'eq' : 0b100,
117 'ne' : 0b101,
118 'so' : 0b110, 'un' : 0b110, # same value
119 'ns' : 0b111, 'nu' : 0b111, # same value
120 }
121 assert encoding in pmap, \
122 "encoding %s for BO Mode not recognised" % encoding
123 return pmap[encoding]
124
125 # partial-decode fail-first mode
126 def decode_ffirst(encoding):
127 if encoding in ['RC1', '~RC1']:
128 return encoding
129 return decode_bo(encoding)
130
131
132 # gets SVP64 ReMap information
133 class SVP64RM:
134 def __init__(self):
135 self.instrs = {}
136 pth = find_wiki_dir()
137 for fname in os.listdir(pth):
138 if fname.startswith("RM"):
139 for entry in get_csv(fname):
140 self.instrs[entry['insn']] = entry
141
142
143 # decodes svp64 assembly listings and creates EXT001 svp64 prefixes
144 class SVP64:
145 def __init__(self, lst):
146 self.lst = lst
147 self.trans = self.translate(lst)
148
149 def __iter__(self):
150 for insn in self.trans:
151 yield insn
152
153 def translate(self, lst):
154 isa = ISA() # reads the v3.0B pseudo-code markdown files
155 svp64 = SVP64RM() # reads the svp64 Remap entries for registers
156 res = []
157 for insn in lst:
158 # find first space, to get opcode
159 ls = insn.split(' ')
160 opcode = ls[0]
161 # now find opcode fields
162 fields = ''.join(ls[1:]).split(',')
163 fields = list(map(str.strip, fields))
164 print ("opcode, fields", ls, opcode, fields)
165
166 # identify if is a svp64 mnemonic
167 if not opcode.startswith('sv.'):
168 res.append(insn) # unaltered
169 continue
170 opcode = opcode[3:] # strip leading "sv."
171
172 # start working on decoding the svp64 op: sv.basev30Bop/vec2/mode
173 opmodes = opcode.split("/") # split at "/"
174 v30b_op = opmodes.pop(0) # first is the v3.0B
175 # check instruction ends with dot
176 rc_mode = v30b_op.endswith('.')
177 if rc_mode:
178 v30b_op = v30b_op[:-1]
179
180 if v30b_op not in isa.instr:
181 raise Exception("opcode %s of '%s' not supported" % \
182 (v30b_op, insn))
183 if v30b_op not in svp64.instrs:
184 raise Exception("opcode %s of '%s' not an svp64 instruction" % \
185 (v30b_op, insn))
186 isa.instr[v30b_op].regs[0]
187 v30b_regs = isa.instr[v30b_op].regs[0]
188 rm = svp64.instrs[v30b_op]
189 print ("v3.0B op", v30b_op, "Rc=1" if rc_mode else '')
190 print ("v3.0B regs", opcode, v30b_regs)
191 print (rm)
192
193 # right. the first thing to do is identify the ordering of
194 # the registers, by name. the EXTRA2/3 ordering is in
195 # rm['0']..rm['3'] but those fields contain the names RA, BB
196 # etc. we have to read the pseudocode to understand which
197 # reg is which in our instruction. sigh.
198
199 # first turn the svp64 rm into a "by name" dict, recording
200 # which position in the RM EXTRA it goes into
201 # also: record if the src or dest was a CR, for sanity-checking
202 # (elwidth overrides on CRs are banned)
203 dest_reg_cr, src_reg_cr = False, False
204 svp64_reg_byname = {}
205 for i in range(4):
206 rfield = rm[str(i)]
207 if not rfield or rfield == '0':
208 continue
209 print ("EXTRA field", i, rfield)
210 rfield = rfield.split(";") # s:RA;d:CR1 etc.
211 for r in rfield:
212 rtype = r[0]
213 r = r[2:] # ignore s: and d:
214 svp64_reg_byname[r] = i # this reg in EXTRA position 0-3
215 # check the regtype (if CR, record that)
216 regtype = get_regtype(r)
217 if regtype in ['CR_3bit', 'CR_5bit']:
218 if rtype == 'd':
219 dest_reg_cr = True
220 if rtype == 'd':
221 src_reg_cr = True
222
223 print ("EXTRA field index, by regname", svp64_reg_byname)
224
225 # okaaay now we identify the field value (opcode N,N,N) with
226 # the pseudo-code info (opcode RT, RA, RB)
227 assert len(fields) == len(v30b_regs), \
228 "length of fields %s must match insn `%s`" % \
229 (str(v30b_regs), insn)
230 opregfields = zip(fields, v30b_regs) # err that was easy
231
232 # now for each of those find its place in the EXTRA encoding
233 extras = OrderedDict()
234 for idx, (field, regname) in enumerate(opregfields):
235 extra = svp64_reg_byname.get(regname, None)
236 regtype = get_regtype(regname)
237 extras[extra] = (idx, field, regname, regtype)
238 print (" ", extra, extras[extra])
239
240 # great! got the extra fields in their associated positions:
241 # also we know the register type. now to create the EXTRA encodings
242 etype = rm['Etype'] # Extra type: EXTRA3/EXTRA2
243 ptype = rm['Ptype'] # Predication type: Twin / Single
244 extra_bits = 0
245 v30b_newfields = []
246 for extra_idx, (idx, field, regname, regtype) in extras.items():
247 # is it a field we don't alter/examine? if so just put it
248 # into newfields
249 if regtype is None:
250 v30b_newfields.append(field)
251
252 # first, decode the field number. "5.v" or "3.s" or "9"
253 field = field.split(".")
254 regmode = 'scalar' # default
255 if len(field) == 2:
256 if field[1] == 's':
257 regmode = 'scalar'
258 elif field[1] == 'v':
259 regmode = 'vector'
260 field = int(field[0]) # actual register number
261 print (" ", regmode, field, end=" ")
262
263 # XXX TODO: the following is a bit of a laborious repeated
264 # mess, which could (and should) easily be parameterised.
265
266 # encode SV-GPR field into extra, v3.0field
267 if regtype == 'GPR':
268 sv_extra, field = get_extra_gpr(etype, regmode, field)
269 # now sanity-check. EXTRA3 is ok, EXTRA2 has limits
270 # (and shrink to a single bit if ok)
271 if etype == 'EXTRA2':
272 if regmode == 'scalar':
273 # range is r0-r63 in increments of 1
274 assert (sv_extra >> 1) == 0, \
275 "scalar GPR %s cannot fit into EXTRA2 %s" % \
276 (regname, str(extras[extra_idx]))
277 # all good: encode as scalar
278 sv_extra = sv_extra & 0b01
279 else:
280 # range is r0-r127 in increments of 4
281 assert sv_extra & 0b01 == 0, \
282 "vector field %s cannot fit into EXTRA2 %s" % \
283 (regname, str(extras[extra_idx]))
284 # all good: encode as vector (bit 2 set)
285 sv_extra = 0b10 | (sv_extra >> 1)
286 elif regmode == 'vector':
287 # EXTRA3 vector bit needs marking
288 sv_extra |= 0b100
289
290 # encode SV-CR 3-bit field into extra, v3.0field
291 elif regtype == 'CR_3bit':
292 sv_extra, field = get_extra_cr_3bit(etype, regmode, field)
293 # now sanity-check (and shrink afterwards)
294 if etype == 'EXTRA2':
295 if regmode == 'scalar':
296 # range is CR0-CR15 in increments of 1
297 assert (sv_extra >> 1) == 0, \
298 "scalar CR %s cannot fit into EXTRA2 %s" % \
299 (regname, str(extras[extra_idx]))
300 # all good: encode as scalar
301 sv_extra = sv_extra & 0b01
302 else:
303 # range is CR0-CR127 in increments of 16
304 assert sv_extra & 0b111 == 0, \
305 "vector CR %s cannot fit into EXTRA2 %s" % \
306 (regname, str(extras[extra_idx]))
307 # all good: encode as vector (bit 2 set)
308 sv_extra = 0b10 | (sv_extra >> 3)
309 else:
310 if regmode == 'scalar':
311 # range is CR0-CR31 in increments of 1
312 assert (sv_extra >> 2) == 0, \
313 "scalar CR %s cannot fit into EXTRA2 %s" % \
314 (regname, str(extras[extra_idx]))
315 # all good: encode as scalar
316 sv_extra = sv_extra & 0b11
317 else:
318 # range is CR0-CR127 in increments of 8
319 assert sv_extra & 0b11 == 0, \
320 "vector CR %s cannot fit into EXTRA2 %s" % \
321 (regname, str(extras[extra_idx]))
322 # all good: encode as vector (bit 3 set)
323 sv_extra = 0b100 | (sv_extra >> 2)
324
325 # encode SV-CR 5-bit field into extra, v3.0field
326 # *sigh* this is the same as 3-bit except the 2 LSBs are
327 # passed through
328 elif regtype == 'CR_5bit':
329 cr_subfield = field & 0b11
330 field = field >> 2 # strip bottom 2 bits
331 sv_extra, field = get_extra_cr_3bit(etype, regmode, field)
332 # now sanity-check (and shrink afterwards)
333 if etype == 'EXTRA2':
334 if regmode == 'scalar':
335 # range is CR0-CR15 in increments of 1
336 assert (sv_extra >> 1) == 0, \
337 "scalar CR %s cannot fit into EXTRA2 %s" % \
338 (regname, str(extras[extra_idx]))
339 # all good: encode as scalar
340 sv_extra = sv_extra & 0b01
341 else:
342 # range is CR0-CR127 in increments of 16
343 assert sv_extra & 0b111 == 0, \
344 "vector CR %s cannot fit into EXTRA2 %s" % \
345 (regname, str(extras[extra_idx]))
346 # all good: encode as vector (bit 2 set)
347 sv_extra = 0b10 | (sv_extra >> 3)
348 else:
349 if regmode == 'scalar':
350 # range is CR0-CR31 in increments of 1
351 assert (sv_extra >> 2) == 0, \
352 "scalar CR %s cannot fit into EXTRA2 %s" % \
353 (regname, str(extras[extra_idx]))
354 # all good: encode as scalar
355 sv_extra = sv_extra & 0b11
356 else:
357 # range is CR0-CR127 in increments of 8
358 assert sv_extra & 0b11 == 0, \
359 "vector CR %s cannot fit into EXTRA2 %s" % \
360 (regname, str(extras[extra_idx]))
361 # all good: encode as vector (bit 3 set)
362 sv_extra = 0b100 | (sv_extra >> 2)
363
364 # reconstruct the actual 5-bit CR field
365 field = (field << 2) | cr_subfield
366
367 # capture the extra field info
368 print ("=>", "%5s" % bin(sv_extra), field)
369 extras[extra_idx] = sv_extra
370
371 # append altered field value to v3.0b
372 v30b_newfields.append(str(field))
373
374 print ("new v3.0B fields", v30b_op, v30b_newfields)
375 print ("extras", extras)
376
377 # rright. now we have all the info. start creating SVP64 RM
378 svp64_rm = 0b0
379
380 # begin with EXTRA fields
381 for idx, sv_extra in extras.items():
382 if idx is None: continue
383 # start at bit 10, work up 2/3 times EXTRA idx
384 offs = 2 if etype == 'EXTRA2' else 3 # 2 or 3 bits
385 svp64_rm |= sv_extra << (10+idx*offs)
386
387 # parts of svp64_rm
388 mmode = 0 # bit 0
389 pmask = 0 # bits 1-3
390 destwid = 0 # bits 4-5
391 srcwid = 0 # bits 6-7
392 subvl = 0 # bits 8-9
393 smask = 0 # bits 16-18 but only for twin-predication
394 mode = 0 # bits 19-23
395
396 has_pmask = False
397 has_smask = False
398
399 saturation = None
400 src_zero = 0
401 dst_zero = 0
402 sv_mode = None
403
404 mapreduce = False
405 mapreduce_crm = False
406 mapreduce_svm = False
407
408 predresult = False
409 failfirst = False
410
411 # ok let's start identifying opcode augmentation fields
412 for encmode in opmodes:
413 # predicate mask (dest)
414 if encmode.startswith("m="):
415 pme = encmode
416 pmmode, pmask = decode_predicate(encmode[2:])
417 mmode = pmmode
418 has_pmask = True
419 # predicate mask (src, twin-pred)
420 elif encmode.startswith("sm="):
421 sme = encmode
422 smmode, smask = decode_predicate(encmode[3:])
423 mmode = smmode
424 has_smask = True
425 # vec2/3/4
426 elif encmode.startswith("vec"):
427 subvl = decode_subvl(encmode[3:])
428 # elwidth
429 elif encmode.startswith("ew="):
430 destwid = decode_elwidth(encmode[3:])
431 elif encmode.startswith("sw="):
432 srcwid = decode_elwidth(encmode[3:])
433 # saturation
434 elif encmode == 'sats':
435 assert sv_mode is None
436 saturation = 1
437 sv_mode = 0b10
438 elif encmode == 'satu':
439 assert sv_mode is None
440 sv_mode = 0b10
441 saturation = 0
442 # predicate zeroing
443 elif encmode == 'sz':
444 src_zero = 1
445 elif encmode == 'dz':
446 dst_zero = 1
447 # failfirst
448 elif encmode.startswith("ff="):
449 assert sv_mode is None
450 sv_mode = 0b01
451 failfirst = decode_ffirst(encmode[3:])
452 # predicate-result, interestingly same as fail-first
453 elif encmode.startswith("pr="):
454 assert sv_mode is None
455 sv_mode = 0b11
456 predresult = decode_ffirst(encmode[3:])
457 # map-reduce mode
458 elif encmode == 'mr':
459 assert sv_mode is None
460 sv_mode = 0b00
461 mapreduce = True
462 elif encmode == 'crm': # CR on map-reduce
463 assert sv_mode is None
464 sv_mode = 0b00
465 mapreduce_crm = True
466 elif encmode == 'svm': # sub-vector mode
467 mapreduce_svm = True
468
469 # sanity-check that 2Pred mask is same mode
470 if has_pmask and has_smask:
471 assert smmode == pmmode, \
472 "predicate masks %s and %s must be same reg type" % \
473 (pme, sme)
474
475 # sanity-check that twin-predication mask only specified in 2P mode
476 if ptype == '1P':
477 assert has_smask == False, \
478 "source-mask can only be specified on Twin-predicate ops"
479
480 # construct the mode field, doing sanity-checking along the way
481
482 if mapreduce_svm:
483 assert sv_mode == 0b00, "sub-vector mode in mapreduce only"
484 assert subvl != 0, "sub-vector mode not possible on SUBVL=1"
485
486 if src_zero:
487 assert has_smask, "src zeroing requires a source predicate"
488 if dst_zero:
489 assert has_pmask, "dest zeroing requires a dest predicate"
490
491 # "normal" mode
492 if sv_mode is None:
493 mode |= (src_zero << 3) | (dst_zero << 4) # predicate zeroing
494 sv_mode = 0b00
495
496 # "mapreduce" modes
497 elif sv_mode == 0b00:
498 mode |= (0b1<<2) # sets mapreduce
499 assert dst_zero == 0, "dest-zero not allowed in mapreduce mode"
500 if mapreduce_crm:
501 mode |= (0b1<<4) # sets CRM mode
502 assert rc_mode, "CRM only allowed when Rc=1"
503 # bit of weird encoding to jam zero-pred or SVM mode in.
504 # SVM mode can be enabled only when SUBVL=2/3/4 (vec2/3/4)
505 if subvl == 0:
506 mode |= (src_zero << 3) # predicate src-zeroing
507 elif mapreduce_svm:
508 mode |= (1 << 3) # SVM mode
509
510 # "failfirst" modes
511 elif sv_mode == 0b01:
512 assert dst_zero == 0, "dest-zero not allowed in failfirst mode"
513 if failfirst == 'RC1':
514 mode |= (0b1<<4) # sets RC1 mode
515 mode |= (src_zero << 3) # predicate src-zeroing
516 assert rc_mode==False, "ffirst RC1 only possible when Rc=0"
517 elif failfirst == '~RC1':
518 mode |= (0b1<<4) # sets RC1 mode...
519 mode |= (src_zero << 3) # predicate src-zeroing
520 mode |= (0b1<<2) # ... with inversion
521 assert rc_mode==False, "ffirst RC1 only possible when Rc=0"
522 else:
523 assert src_zero == 0, "src-zero not allowed in ffirst BO"
524 assert rc_mode, "ffirst BO only possible when Rc=1"
525 mode |= (failfirst << 2) # set BO
526
527 # "saturation" modes
528 elif sv_mode == 0b10:
529 mode |= (src_zero << 3) | (dst_zero << 4) # predicate zeroing
530 mode |= (saturation<<2) # sets signed/unsigned saturation
531
532 # "predicate-result" modes. err... code-duplication from ffirst
533 elif sv_mode == 0b11:
534 assert dst_zero == 0, "dest-zero not allowed in predresult mode"
535 if predresult == 'RC1':
536 mode |= (0b1<<4) # sets RC1 mode
537 mode |= (src_zero << 3) # predicate src-zeroing
538 assert rc_mode==False, "pr-mode RC1 only possible when Rc=0"
539 elif predresult == '~RC1':
540 mode |= (0b1<<4) # sets RC1 mode...
541 mode |= (src_zero << 3) # predicate src-zeroing
542 mode |= (0b1<<2) # ... with inversion
543 assert rc_mode==False, "pr-mode RC1 only possible when Rc=0"
544 else:
545 assert src_zero == 0, "src-zero not allowed in pr-mode BO"
546 assert rc_mode, "pr-mode BO only possible when Rc=1"
547 mode |= (predresult << 2) # set BO
548
549 # whewww.... modes all done :)
550 # now put into svp64_rm
551 mode |= sv_mode
552 svp64_rm |= (mode << 19) # mode: bits 19-23
553
554 # put in predicate masks into svp64_rm
555 if ptype == '2P':
556 svp64_rm |= (smask << 16) # source pred: bits 16-18
557 svp64_rm |= (mmode) # mask mode: bit 0
558 svp64_rm |= (pmask << 1) # 1-pred: bits 1-3
559
560 # and subvl
561 svp64_rm += (subvl << 8) # subvl: bits 8-9
562
563 # put in elwidths
564 svp64_rm += (srcwid << 6) # srcwid: bits 6-7
565 svp64_rm += (destwid << 4) # destwid: bits 4-5
566
567 # nice debug printout. (and now for something completely different)
568 # https://youtu.be/u0WOIwlXE9g?t=146
569 print ("svp64_rm", hex(svp64_rm), bin(svp64_rm))
570 print (" mmode 0 :", bin(mmode))
571 print (" pmask 1-3 :", bin(pmask))
572 print (" dstwid 4-5 :", bin(destwid))
573 print (" srcwid 6-7 :", bin(srcwid))
574 print (" subvl 8-9 :", bin(subvl))
575 print (" mode 19-23:", bin(mode))
576 offs = 2 if etype == 'EXTRA2' else 3 # 2 or 3 bits
577 for idx, sv_extra in extras.items():
578 if idx is None: continue
579 start = (10+idx*offs)
580 end = start + offs-1
581 print (" extra%d %2d-%2d:" % (idx, start, end),
582 bin(sv_extra))
583 if ptype == '2P':
584 print (" smask 16-17:", bin(smask))
585 print ()
586
587 return res
588
589 if __name__ == '__main__':
590 isa = SVP64(['slw 3, 1, 4',
591 'extsw 5, 3',
592 'sv.extsw 5, 3',
593 'sv.cmpi 5, 1, 3, 2',
594 'sv.setb 5, 31',
595 'sv.isel 64.v, 3, 2, 65.v',
596 'sv.setb/m=r3/sm=1<<r3 5, 31',
597 'sv.setb/vec2 5, 31',
598 'sv.setb/sw=8/ew=16 5, 31',
599 'sv.extsw./ff=eq 5, 31',
600 'sv.extsw./satu/sz/dz/sm=r3/m=r3 5, 31',
601 'sv.extsw./pr=eq 5.v, 31',
602 ])
603 csvs = SVP64RM()