src/soc/sv/trans/svp64.py

   1 # SPDX-License-Identifier: LGPLv3+
   2 # Copyright (C) 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   3 # Funded by NLnet http://nlnet.nl
   4
   5 """SVP64 OpenPOWER v3.0B assembly translator
   6
   7 This class takes raw svp64 assembly mnemonics (aliases excluded) and
   8 creates an EXT001-encoded "svp64 prefix" followed by a v3.0B opcode.
   9
  10 It is very simple and straightforward, the only weirdness being the
  11 extraction of the register information and conversion to v3.0B numbering.
  12
  13 Encoding format of svp64: https://libre-soc.org/openpower/sv/svp64/
  14 Bugtracker: https://bugs.libre-soc.org/show_bug.cgi?id=578
  15 """
  16
  17 import os, sys
  18 from collections import OrderedDict
  19
  20 from soc.decoder.isa.caller import (SVP64PrefixFields, SV64P_MAJOR_SIZE,
  21                                     SV64P_PID_SIZE, SVP64RMFields,
  22                                     SVP64RM_EXTRA2_SPEC_SIZE,
  23                                     SVP64RM_EXTRA3_SPEC_SIZE,
  24                                     SVP64RM_MODE_SIZE, SVP64RM_SMASK_SIZE,
  25                                     SVP64RM_MMODE_SIZE, SVP64RM_MASK_SIZE,
  26                                     SVP64RM_SUBVL_SIZE, SVP64RM_EWSRC_SIZE,
  27                                     SVP64RM_ELWIDTH_SIZE)
  28 from soc.decoder.pseudo.pagereader import ISA
  29 from soc.decoder.power_svp64 import SVP64RM, get_regtype, decode_extra
  30 from soc.decoder.selectable_int import SelectableInt
  31 from soc.consts import SVP64MODE
  32
  33
  34 # decode GPR into sv extra
  35 def  get_extra_gpr(etype, regmode, field):
  36     if regmode == 'scalar':
  37         # cut into 2-bits 5-bits SS FFFFF
  38         sv_extra = field >> 5
  39         field = field & 0b11111
  40     else:
  41         # cut into 5-bits 2-bits FFFFF SS
  42         sv_extra = field & 0b11
  43         field = field >> 2
  44     return sv_extra, field
  45
  46
  47 # decode 3-bit CR into sv extra
  48 def  get_extra_cr_3bit(etype, regmode, field):
  49     if regmode == 'scalar':
  50         # cut into 2-bits 3-bits SS FFF
  51         sv_extra = field >> 3
  52         field = field & 0b111
  53     else:
  54         # cut into 3-bits 4-bits FFF SSSS but will cut 2 zeros off later
  55         sv_extra = field & 0b1111
  56         field = field >> 4
  57     return sv_extra, field
  58
  59
  60 # decodes SUBVL
  61 def decode_subvl(encoding):
  62     pmap = {'2': 0b01, '3': 0b10, '4': 0b11}
  63     assert encoding in pmap, \
  64         "encoding %s for SUBVL not recognised" % encoding
  65     return pmap[encoding]
  66
  67
  68 # decodes elwidth
  69 def decode_elwidth(encoding):
  70     pmap = {'8': 0b11, '16': 0b10, '32': 0b01}
  71     assert encoding in pmap, \
  72         "encoding %s for elwidth not recognised" % encoding
  73     return pmap[encoding]
  74
  75
  76 # decodes predicate register encoding
  77 def decode_predicate(encoding):
  78     pmap = { # integer
  79             '1<<r3': (0, 0b001),
  80             'r3'   : (0, 0b010),
  81             '~r3'   : (0, 0b011),
  82             'r10'   : (0, 0b100),
  83             '~r10'  : (0, 0b101),
  84             'r30'   : (0, 0b110),
  85             '~r30'  : (0, 0b111),
  86             # CR
  87             'lt'    : (1, 0b000),
  88             'nl'    : (1, 0b001), 'ge'    : (1, 0b001), # same value
  89             'gt'    : (1, 0b010),
  90             'ng'    : (1, 0b011), 'le'    : (1, 0b011), # same value
  91             'eq'    : (1, 0b100),
  92             'ne'    : (1, 0b101),
  93             'so'    : (1, 0b110), 'un'    : (1, 0b110), # same value
  94             'ns'    : (1, 0b111), 'nu'    : (1, 0b111), # same value
  95            }
  96     assert encoding in pmap, \
  97         "encoding %s for predicate not recognised" % encoding
  98     return pmap[encoding]
  99
 100
 101 # decodes "Mode" in similar way to BO field (supposed to, anyway)
 102 def decode_bo(encoding):
 103     pmap = { # TODO: double-check that these are the same as Branch BO
 104             'lt'    : 0b000,
 105             'nl'    : 0b001, 'ge'    : 0b001, # same value
 106             'gt'    : 0b010,
 107             'ng'    : 0b011, 'le'    : 0b011, # same value
 108             'eq'    : 0b100,
 109             'ne'    : 0b101,
 110             'so'    : 0b110, 'un'    : 0b110, # same value
 111             'ns'    : 0b111, 'nu'    : 0b111, # same value
 112            }
 113     assert encoding in pmap, \
 114         "encoding %s for BO Mode not recognised" % encoding
 115     return pmap[encoding]
 116
 117 # partial-decode fail-first mode
 118 def decode_ffirst(encoding):
 119     if encoding in ['RC1', '~RC1']:
 120         return encoding
 121     return decode_bo(encoding)
 122
 123
 124 def decode_reg(field):
 125     # decode the field number. "5.v" or "3.s" or "9"
 126     field = field.split(".")
 127     regmode = 'scalar' # default
 128     if len(field) == 2:
 129         if field[1] == 's':
 130             regmode = 'scalar'
 131         elif field[1] == 'v':
 132             regmode = 'vector'
 133     field = int(field[0]) # actual register number
 134     return field, regmode
 135
 136
 137 def decode_imm(field):
 138     ldst_imm = "(" in field and field[-1] == ')'
 139     if ldst_imm:
 140         return field[:-1].split("(")
 141     else:
 142         return None, field
 143
 144 # decodes svp64 assembly listings and creates EXT001 svp64 prefixes
 145 class SVP64Asm:
 146     def __init__(self, lst, bigendian=False):
 147         self.lst = lst
 148         self.trans = self.translate(lst)
 149         assert bigendian == False, "error, bigendian not supported yet"
 150
 151     def __iter__(self):
 152         yield from self.trans
 153
 154     def translate(self, lst):
 155         isa = ISA() # reads the v3.0B pseudo-code markdown files
 156         svp64 = SVP64RM() # reads the svp64 Remap entries for registers
 157         for insn in lst:
 158             # find first space, to get opcode
 159             ls = insn.split(' ')
 160             opcode = ls[0]
 161             # now find opcode fields
 162             fields = ''.join(ls[1:]).split(',')
 163             fields = list(map(str.strip, fields))
 164             print ("opcode, fields", ls, opcode, fields)
 165
 166             # sigh have to do setvl here manually for now...
 167             if opcode in ["setvl", "setvl."]:
 168                 insn = 22 << (31-5)          # opcode 22, bits 0-5
 169                 fields = list(map(int, fields))
 170                 insn |= fields[0] << (31-10) # RT       , bits 6-10
 171                 insn |= fields[1] << (31-15) # RA       , bits 11-15
 172                 insn |= fields[2] << (31-23) # SVi      , bits 16-23
 173                 insn |= fields[3] << (31-24) # vs       , bit  24
 174                 insn |= fields[4] << (31-25) # ms       , bit  25
 175                 insn |= 0b00000   << (31-30) # XO       , bits 26..30
 176                 if opcode == 'setvl.':
 177                     insn |= 1 << (31-31)     # Rc=1     , bit 31
 178                 print ("setvl", bin(insn))
 179                 yield ".long 0x%x" % insn
 180                 continue
 181
 182             # identify if is a svp64 mnemonic
 183             if not opcode.startswith('sv.'):
 184                 yield insn  # unaltered
 185                 continue
 186             opcode = opcode[3:] # strip leading "sv"
 187
 188             # start working on decoding the svp64 op: sv.basev30Bop/vec2/mode
 189             opmodes = opcode.split("/") # split at "/"
 190             v30b_op = opmodes.pop(0)    # first is the v3.0B
 191             # check instruction ends with dot
 192             rc_mode = v30b_op.endswith('.')
 193             if rc_mode:
 194                 v30b_op = v30b_op[:-1]
 195
 196             if v30b_op not in isa.instr:
 197                 raise Exception("opcode %s of '%s' not supported" % \
 198                                 (v30b_op, insn))
 199             if v30b_op not in svp64.instrs:
 200                 raise Exception("opcode %s of '%s' not an svp64 instruction" % \
 201                                 (v30b_op, insn))
 202             v30b_regs = isa.instr[v30b_op].regs[0] # get regs info "RT, RA, RB"
 203             rm = svp64.instrs[v30b_op]             # one row of the svp64 RM CSV
 204             print ("v3.0B op", v30b_op, "Rc=1" if rc_mode else '')
 205             print ("v3.0B regs", opcode, v30b_regs)
 206             print (rm)
 207
 208             # right.  the first thing to do is identify the ordering of
 209             # the registers, by name.  the EXTRA2/3 ordering is in
 210             # rm['0']..rm['3'] but those fields contain the names RA, BB
 211             # etc.  we have to read the pseudocode to understand which
 212             # reg is which in our instruction. sigh.
 213
 214             # first turn the svp64 rm into a "by name" dict, recording
 215             # which position in the RM EXTRA it goes into
 216             # also: record if the src or dest was a CR, for sanity-checking
 217             # (elwidth overrides on CRs are banned)
 218             decode = decode_extra(rm)
 219             dest_reg_cr, src_reg_cr, svp64_src, svp64_dest = decode
 220             svp64_reg_byname = {}
 221             svp64_reg_byname.update(svp64_src)
 222             svp64_reg_byname.update(svp64_dest)
 223
 224             print ("EXTRA field index, by regname", svp64_reg_byname)
 225
 226             # okaaay now we identify the field value (opcode N,N,N) with
 227             # the pseudo-code info (opcode RT, RA, RB)
 228             assert len(fields) == len(v30b_regs), \
 229                 "length of fields %s must match insn `%s`" % \
 230                         (str(v30b_regs), insn)
 231             opregfields = zip(fields, v30b_regs) # err that was easy
 232
 233             # now for each of those find its place in the EXTRA encoding
 234             extras = OrderedDict()
 235             for idx, (field, regname) in enumerate(opregfields):
 236                 imm, regname = decode_imm(regname)
 237                 extra = svp64_reg_byname.get(regname, None)
 238                 rtype = get_regtype(regname)
 239                 extras[extra] = (idx, field, regname, rtype, imm)
 240                 print ("    ", extra, extras[extra])
 241
 242             # great! got the extra fields in their associated positions:
 243             # also we know the register type. now to create the EXTRA encodings
 244             etype = rm['Etype'] # Extra type: EXTRA3/EXTRA2
 245             ptype = rm['Ptype'] # Predication type: Twin / Single
 246             extra_bits = 0
 247             v30b_newfields = []
 248             for extra_idx, (idx, field, rname, rtype, iname) in extras.items():
 249                 # is it a field we don't alter/examine?  if so just put it
 250                 # into newfields
 251                 if rtype is None:
 252                     v30b_newfields.append(field)
 253
 254                 # identify if this is a ld/st immediate(reg) thing
 255                 ldst_imm = "(" in field and field[-1] == ')'
 256                 if ldst_imm:
 257                     immed, field = field[:-1].split("(")
 258
 259                 field, regmode = decode_reg(field)
 260                 print ("    ", extra_idx, rname, rtype,
 261                                regmode, iname, field, end=" ")
 262
 263                 # see Mode field https://libre-soc.org/openpower/sv/svp64/
 264                 # XXX TODO: the following is a bit of a laborious repeated
 265                 # mess, which could (and should) easily be parameterised.
 266                 # XXX also TODO: the LD/ST modes which are different
 267                 # https://libre-soc.org/openpower/sv/ldst/
 268
 269                 # encode SV-GPR field into extra, v3.0field
 270                 if rtype == 'GPR':
 271                     sv_extra, field = get_extra_gpr(etype, regmode, field)
 272                     # now sanity-check. EXTRA3 is ok, EXTRA2 has limits
 273                     # (and shrink to a single bit if ok)
 274                     if etype == 'EXTRA2':
 275                         if regmode == 'scalar':
 276                             # range is r0-r63 in increments of 1
 277                             assert (sv_extra >> 1) == 0, \
 278                                 "scalar GPR %s cannot fit into EXTRA2 %s" % \
 279                                     (rname, str(extras[extra_idx]))
 280                             # all good: encode as scalar
 281                             sv_extra = sv_extra & 0b01
 282                         else:
 283                             # range is r0-r127 in increments of 4
 284                             assert sv_extra & 0b01 == 0, \
 285                                 "vector field %s cannot fit into EXTRA2 %s" % \
 286                                     (rname, str(extras[extra_idx]))
 287                             # all good: encode as vector (bit 2 set)
 288                             sv_extra = 0b10 | (sv_extra >> 1)
 289                     elif regmode == 'vector':
 290                         # EXTRA3 vector bit needs marking
 291                         sv_extra |= 0b100
 292
 293                 # encode SV-CR 3-bit field into extra, v3.0field
 294                 elif rtype == 'CR_3bit':
 295                     sv_extra, field = get_extra_cr_3bit(etype, regmode, field)
 296                     # now sanity-check (and shrink afterwards)
 297                     if etype == 'EXTRA2':
 298                         if regmode == 'scalar':
 299                             # range is CR0-CR15 in increments of 1
 300                             assert (sv_extra >> 1) == 0, \
 301                                 "scalar CR %s cannot fit into EXTRA2 %s" % \
 302                                     (rname, str(extras[extra_idx]))
 303                             # all good: encode as scalar
 304                             sv_extra = sv_extra & 0b01
 305                         else:
 306                             # range is CR0-CR127 in increments of 16
 307                             assert sv_extra & 0b111 == 0, \
 308                                 "vector CR %s cannot fit into EXTRA2 %s" % \
 309                                     (rname, str(extras[extra_idx]))
 310                             # all good: encode as vector (bit 2 set)
 311                             sv_extra = 0b10 | (sv_extra >> 3)
 312                     else:
 313                         if regmode == 'scalar':
 314                             # range is CR0-CR31 in increments of 1
 315                             assert (sv_extra >> 2) == 0, \
 316                                 "scalar CR %s cannot fit into EXTRA2 %s" % \
 317                                     (rname, str(extras[extra_idx]))
 318                             # all good: encode as scalar
 319                             sv_extra = sv_extra & 0b11
 320                         else:
 321                             # range is CR0-CR127 in increments of 8
 322                             assert sv_extra & 0b11 == 0, \
 323                                 "vector CR %s cannot fit into EXTRA2 %s" % \
 324                                     (rname, str(extras[extra_idx]))
 325                             # all good: encode as vector (bit 3 set)
 326                             sv_extra = 0b100 | (sv_extra >> 2)
 327
 328                 # encode SV-CR 5-bit field into extra, v3.0field
 329                 # *sigh* this is the same as 3-bit except the 2 LSBs are
 330                 # passed through
 331                 elif rtype == 'CR_5bit':
 332                     cr_subfield = field & 0b11
 333                     field = field >> 2 # strip bottom 2 bits
 334                     sv_extra, field = get_extra_cr_3bit(etype, regmode, field)
 335                     # now sanity-check (and shrink afterwards)
 336                     if etype == 'EXTRA2':
 337                         if regmode == 'scalar':
 338                             # range is CR0-CR15 in increments of 1
 339                             assert (sv_extra >> 1) == 0, \
 340                                 "scalar CR %s cannot fit into EXTRA2 %s" % \
 341                                     (rname, str(extras[extra_idx]))
 342                             # all good: encode as scalar
 343                             sv_extra = sv_extra & 0b01
 344                         else:
 345                             # range is CR0-CR127 in increments of 16
 346                             assert sv_extra & 0b111 == 0, \
 347                                 "vector CR %s cannot fit into EXTRA2 %s" % \
 348                                     (rname, str(extras[extra_idx]))
 349                             # all good: encode as vector (bit 2 set)
 350                             sv_extra = 0b10 | (sv_extra >> 3)
 351                     else:
 352                         if regmode == 'scalar':
 353                             # range is CR0-CR31 in increments of 1
 354                             assert (sv_extra >> 2) == 0, \
 355                                 "scalar CR %s cannot fit into EXTRA2 %s" % \
 356                                     (rname, str(extras[extra_idx]))
 357                             # all good: encode as scalar
 358                             sv_extra = sv_extra & 0b11
 359                         else:
 360                             # range is CR0-CR127 in increments of 8
 361                             assert sv_extra & 0b11 == 0, \
 362                                 "vector CR %s cannot fit into EXTRA2 %s" % \
 363                                     (rname, str(extras[extra_idx]))
 364                             # all good: encode as vector (bit 3 set)
 365                             sv_extra = 0b100 | (sv_extra >> 2)
 366
 367                     # reconstruct the actual 5-bit CR field
 368                     field = (field << 2) | cr_subfield
 369
 370                 # capture the extra field info
 371                 print ("=>", "%5s" % bin(sv_extra), field)
 372                 extras[extra_idx] = sv_extra
 373
 374                 # append altered field value to v3.0b, differs for LDST
 375                 if ldst_imm:
 376                     v30b_newfields.append(("%s(%s)" % (immed, str(field))))
 377                 else:
 378                     v30b_newfields.append(str(field))
 379
 380             print ("new v3.0B fields", v30b_op, v30b_newfields)
 381             print ("extras", extras)
 382
 383             # rright.  now we have all the info. start creating SVP64 RM
 384             svp64_rm = SVP64RMFields()
 385
 386             # begin with EXTRA fields
 387             for idx, sv_extra in extras.items():
 388                 if idx is None: continue
 389                 if etype == 'EXTRA2':
 390                     svp64_rm.extra2[idx].eq(
 391                         SelectableInt(sv_extra, SVP64RM_EXTRA2_SPEC_SIZE))
 392                 else:
 393                     svp64_rm.extra3[idx].eq(
 394                         SelectableInt(sv_extra, SVP64RM_EXTRA3_SPEC_SIZE))
 395
 396             # parts of svp64_rm
 397             mmode = 0  # bit 0
 398             pmask = 0  # bits 1-3
 399             destwid = 0 # bits 4-5
 400             srcwid = 0 # bits 6-7
 401             subvl = 0   # bits 8-9
 402             smask = 0 # bits 16-18 but only for twin-predication
 403             mode = 0 # bits 19-23
 404
 405             mask_m_specified = False
 406             has_pmask = False
 407             has_smask = False
 408
 409             saturation = None
 410             src_zero = 0
 411             dst_zero = 0
 412             sv_mode = None
 413
 414             mapreduce = False
 415             mapreduce_crm = False
 416             mapreduce_svm = False
 417
 418             predresult = False
 419             failfirst = False
 420
 421             # ok let's start identifying opcode augmentation fields
 422             for encmode in opmodes:
 423                 # predicate mask (src and dest)
 424                 if encmode.startswith("m="):
 425                     mask_m_specified = True
 426                     pme = encmode
 427                     pmmode, pmask = decode_predicate(encmode[2:])
 428                     smmode, smask = pmmode, pmask
 429                     mmode = pmmode
 430                     has_pmask = True
 431                     has_smask = True
 432                 # predicate mask (dest)
 433                 elif encmode.startswith("dm="):
 434                     pme = encmode
 435                     pmmode, pmask = decode_predicate(encmode[3:])
 436                     mmode = pmmode
 437                     has_pmask = True
 438                 # predicate mask (src, twin-pred)
 439                 elif encmode.startswith("sm="):
 440                     sme = encmode
 441                     smmode, smask = decode_predicate(encmode[3:])
 442                     mmode = smmode
 443                     has_smask = True
 444                 # vec2/3/4
 445                 elif encmode.startswith("vec"):
 446                     subvl = decode_subvl(encmode[3:])
 447                 # elwidth
 448                 elif encmode.startswith("ew="):
 449                     destwid = decode_elwidth(encmode[3:])
 450                 elif encmode.startswith("sw="):
 451                     srcwid = decode_elwidth(encmode[3:])
 452                 # saturation
 453                 elif encmode == 'sats':
 454                     assert sv_mode is None
 455                     saturation = 1
 456                     sv_mode = 0b10
 457                 elif encmode == 'satu':
 458                     assert sv_mode is None
 459                     sv_mode = 0b10
 460                     saturation = 0
 461                 # predicate zeroing
 462                 elif encmode == 'sz':
 463                     src_zero = 1
 464                 elif encmode == 'dz':
 465                     dst_zero = 1
 466                 # failfirst
 467                 elif encmode.startswith("ff="):
 468                     assert sv_mode is None
 469                     sv_mode = 0b01
 470                     failfirst = decode_ffirst(encmode[3:])
 471                 # predicate-result, interestingly same as fail-first
 472                 elif encmode.startswith("pr="):
 473                     assert sv_mode is None
 474                     sv_mode = 0b11
 475                     predresult = decode_ffirst(encmode[3:])
 476                 # map-reduce mode
 477                 elif encmode == 'mr':
 478                     assert sv_mode is None
 479                     sv_mode = 0b00
 480                     mapreduce = True
 481                 elif encmode == 'crm': # CR on map-reduce
 482                     assert sv_mode is None
 483                     sv_mode = 0b00
 484                     mapreduce_crm = True
 485                 elif encmode == 'svm': # sub-vector mode
 486                     mapreduce_svm = True
 487
 488             # sanity-check that 2Pred mask is same mode
 489             if has_pmask and has_smask:
 490                 assert smmode == pmmode, \
 491                     "predicate masks %s and %s must be same reg type" % \
 492                         (pme, sme)
 493
 494             # sanity-check that twin-predication mask only specified in 2P mode
 495             if not mask_m_specified and ptype == '1P':
 496                 assert has_smask == False, \
 497                     "source-mask can only be specified on Twin-predicate ops"
 498
 499             # construct the mode field, doing sanity-checking along the way
 500
 501             if mapreduce_svm:
 502                 assert sv_mode == 0b00, "sub-vector mode in mapreduce only"
 503                 assert subvl != 0, "sub-vector mode not possible on SUBVL=1"
 504
 505             if src_zero:
 506                 assert has_smask, "src zeroing requires a source predicate"
 507             if dst_zero:
 508                 assert has_pmask, "dest zeroing requires a dest predicate"
 509
 510             # "normal" mode
 511             if sv_mode is None:
 512                 mode |= src_zero << SVP64MODE.SZ # predicate zeroing
 513                 mode |= dst_zero << SVP64MODE.DZ # predicate zeroing
 514                 sv_mode = 0b00
 515
 516             # "mapreduce" modes
 517             elif sv_mode == 0b00:
 518                 mode |= (0b1<<SVP64MODE.REDUCE) # sets mapreduce
 519                 assert dst_zero == 0, "dest-zero not allowed in mapreduce mode"
 520                 if mapreduce_crm:
 521                     mode |= (0b1<<SVP64MODE.CRM) # sets CRM mode
 522                     assert rc_mode, "CRM only allowed when Rc=1"
 523                 # bit of weird encoding to jam zero-pred or SVM mode in.
 524                 # SVM mode can be enabled only when SUBVL=2/3/4 (vec2/3/4)
 525                 if subvl == 0:
 526                     mode |= dst_zero << SVP64MODE.DZ # predicate zeroing
 527                 elif mapreduce_svm:
 528                     mode |= (0b1<<SVP64MODE.SVM) # sets SVM mode
 529
 530             # "failfirst" modes
 531             elif sv_mode == 0b01:
 532                 assert src_zero == 0, "dest-zero not allowed in failfirst mode"
 533                 if failfirst == 'RC1':
 534                     mode |= (0b1<<SVP64MODE.RC1) # sets RC1 mode
 535                     mode |= (dst_zero << SVP64MODE.DZ) # predicate dst-zeroing
 536                     assert rc_mode==False, "ffirst RC1 only possible when Rc=0"
 537                 elif failfirst == '~RC1':
 538                     mode |= (0b1<<SVP64MODE.RC1) # sets RC1 mode
 539                     mode |= (dst_zero << SVP64MODE.DZ) # predicate dst-zeroing
 540                     mode |= (0b1<<SVP64MODE.INV) # ... with inversion
 541                     assert rc_mode==False, "ffirst RC1 only possible when Rc=0"
 542                 else:
 543                     assert dst_zero == 0, "dst-zero not allowed in ffirst BO"
 544                     assert rc_mode, "ffirst BO only possible when Rc=1"
 545                     mode |= (failfirst << SVP64MODE.BO_LSB) # set BO
 546
 547             # "saturation" modes
 548             elif sv_mode == 0b10:
 549                 mode |= src_zero << SVP64MODE.SZ # predicate zeroing
 550                 mode |= dst_zero << SVP64MODE.DZ # predicate zeroing
 551                 mode |= (saturation << SVP64MODE.N) # signed/unsigned saturation
 552
 553             # "predicate-result" modes.  err... code-duplication from ffirst
 554             elif sv_mode == 0b11:
 555                 assert src_zero == 0, "dest-zero not allowed in predresult mode"
 556                 if predresult == 'RC1':
 557                     mode |= (0b1<<SVP64MODE.RC1) # sets RC1 mode
 558                     mode |= (dst_zero << SVP64MODE.DZ) # predicate dst-zeroing
 559                     assert rc_mode==False, "pr-mode RC1 only possible when Rc=0"
 560                 elif predresult == '~RC1':
 561                     mode |= (0b1<<SVP64MODE.RC1) # sets RC1 mode
 562                     mode |= (dst_zero << SVP64MODE.DZ) # predicate dst-zeroing
 563                     mode |= (0b1<<SVP64MODE.INV) # ... with inversion
 564                     assert rc_mode==False, "pr-mode RC1 only possible when Rc=0"
 565                 else:
 566                     assert dst_zero == 0, "dst-zero not allowed in pr-mode BO"
 567                     assert rc_mode, "pr-mode BO only possible when Rc=1"
 568                     mode |= (predresult << SVP64MODE.BO_LSB) # set BO
 569
 570             # whewww.... modes all done :)
 571             # now put into svp64_rm
 572             mode |= sv_mode
 573             # mode: bits 19-23
 574             svp64_rm.mode.eq(SelectableInt(mode, SVP64RM_MODE_SIZE))
 575
 576             # put in predicate masks into svp64_rm
 577             if ptype == '2P':
 578                 # source pred: bits 16-18
 579                 svp64_rm.smask.eq(SelectableInt(smask, SVP64RM_SMASK_SIZE))
 580             # mask mode: bit 0
 581             svp64_rm.mmode.eq(SelectableInt(mmode, SVP64RM_MMODE_SIZE))
 582             # 1-pred: bits 1-3
 583             svp64_rm.mask.eq(SelectableInt(pmask, SVP64RM_MASK_SIZE))
 584
 585             # and subvl: bits 8-9
 586             svp64_rm.subvl.eq(SelectableInt(subvl, SVP64RM_SUBVL_SIZE))
 587
 588             # put in elwidths
 589             # srcwid: bits 6-7
 590             svp64_rm.ewsrc.eq(SelectableInt(srcwid, SVP64RM_EWSRC_SIZE))
 591             # destwid: bits 4-5
 592             svp64_rm.elwidth.eq(SelectableInt(destwid, SVP64RM_ELWIDTH_SIZE))
 593
 594             # nice debug printout. (and now for something completely different)
 595             # https://youtu.be/u0WOIwlXE9g?t=146
 596             svp64_rm_value = svp64_rm.spr.value
 597             print ("svp64_rm", hex(svp64_rm_value), bin(svp64_rm_value))
 598             print ("    mmode  0    :", bin(mmode))
 599             print ("    pmask  1-3  :", bin(pmask))
 600             print ("    dstwid 4-5  :", bin(destwid))
 601             print ("    srcwid 6-7  :", bin(srcwid))
 602             print ("    subvl  8-9  :", bin(subvl))
 603             print ("    mode   19-23:", bin(mode))
 604             offs = 2 if etype == 'EXTRA2' else 3 # 2 or 3 bits
 605             for idx, sv_extra in extras.items():
 606                 if idx is None: continue
 607                 start = (10+idx*offs)
 608                 end = start + offs-1
 609                 print ("    extra%d %2d-%2d:" % (idx, start, end),
 610                         bin(sv_extra))
 611             if ptype == '2P':
 612                 print ("    smask  16-17:", bin(smask))
 613             print ()
 614
 615             # first, construct the prefix from its subfields
 616             svp64_prefix = SVP64PrefixFields()
 617             svp64_prefix.major.eq(SelectableInt(0x1, SV64P_MAJOR_SIZE))
 618             svp64_prefix.pid.eq(SelectableInt(0b11, SV64P_PID_SIZE))
 619             svp64_prefix.rm.eq(svp64_rm.spr)
 620
 621             # fiinally yield the svp64 prefix and the thingy.  v3.0b opcode
 622             rc = '.' if rc_mode else ''
 623             yield ".long 0x%x" % svp64_prefix.insn.value
 624             yield "%s %s" % (v30b_op+rc, ", ".join(v30b_newfields))
 625             print ("new v3.0B fields", v30b_op, v30b_newfields)
 626
 627 if __name__ == '__main__':
 628     lst = ['slw 3, 1, 4',
 629                  'extsw 5, 3',
 630                  'sv.extsw 5, 3',
 631                  'sv.cmpi 5, 1, 3, 2',
 632                  'sv.setb 5, 31',
 633                  'sv.isel 64.v, 3, 2, 65.v',
 634                  'sv.setb/pm=r3/sm=1<<r3 5, 31',
 635                  'sv.setb/m=r3 5, 31',
 636                  'sv.setb/vec2 5, 31',
 637                  'sv.setb/sw=8/ew=16 5, 31',
 638                  'sv.extsw./ff=eq 5, 31',
 639                  'sv.extsw./satu/sz/dz/sm=r3/m=r3 5, 31',
 640                  'sv.extsw./pr=eq 5.v, 31',
 641                  'sv.add. 5.v, 2.v, 1.v',
 642                  'sv.add./m=r3 5.v, 2.v, 1.v',
 643                 ]
 644     lst += [
 645                  'sv.stw 5.v, 4(1.v)',
 646                  'sv.ld 5.v, 4(1.v)',
 647                  'setvl. 2, 3, 4, 1, 1',
 648           ]
 649     isa = SVP64Asm(lst)
 650     print ("list", list(isa))
 651     csvs = SVP64RM()