541306f2efe06e9d310041e5f251a38fbb27c68b
[soc.git] / src / soc / sv / trans / svp64.py
1 # SPDX-License-Identifier: LGPLv3+
2 # Copyright (C) 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Funded by NLnet http://nlnet.nl
4
5 """SVP64 OpenPOWER v3.0B assembly translator
6
7 This class takes raw svp64 assembly mnemonics (aliases excluded) and
8 creates an EXT001-encoded "svp64 prefix" followed by a v3.0B opcode.
9 It is very simple
10 """
11
12 from soc.decoder.pseudo.pagereader import ISA
13
14
15 def is_CR_3bit(regname):
16 return regname in ['BF', 'BFA']
17
18 def is_CR_5bit(regname):
19 return regname in ['BA', 'BB', 'BC', 'BI', 'BT']
20
21 def is_GPR(regname):
22 return regname in ['RA', 'RB', 'RC', 'RS', 'RT']
23
24
25 class SVP64:
26 def __init__(self, lst):
27 self.lst = lst
28 self.trans = self.translate(lst)
29
30 def __iter__(self):
31 for insn in self.trans:
32 yield insn
33
34 def translate(self, lst):
35 isa = ISA() # reads the v3.0B pseudo-code markdown files
36 res = []
37 for insn in lst:
38 # find first space, to get opcode
39 ls = insn.split(' ')
40 opcode = ls[0]
41 # now find opcode fields
42 fields = ''.join(ls[1:]).split(',')
43 fields = list(map(str.strip, fields))
44 print (opcode, fields)
45
46 # identify if is a svp64 mnemonic
47 if not opcode.startswith('sv.'):
48 res.append(insn) # unaltered
49 continue
50
51 # start working on decoding the svp64 op: sv.baseop.vec2.mode
52 opmodes = opcode.split(".")[1:] # strip leading "sv."
53 v30b_op = opmodes.pop(0) # first is the v3.0B
54 if v30b_op not in isa.instr:
55 raise Exception("opcode %s of '%s' not supported" % \
56 (v30b_op, insn))
57
58 return res
59
60 if __name__ == '__main__':
61 isa = SVP64(['slw 3, 1, 4',
62 'extsw 5, 3'])
63