1 # SPDX-License-Identifier: LGPLv3+
2 # Copyright (C) 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Funded by NLnet http://nlnet.nl
5 """SVP64 OpenPOWER v3.0B assembly translator
7 This class takes raw svp64 assembly mnemonics (aliases excluded) and
8 creates an EXT001-encoded "svp64 prefix" followed by a v3.0B opcode.
12 from soc
.decoder
.pseudo
.pagereader
import ISA
15 def is_CR_3bit(regname
):
16 return regname
in ['BF', 'BFA']
18 def is_CR_5bit(regname
):
19 return regname
in ['BA', 'BB', 'BC', 'BI', 'BT']
22 return regname
in ['RA', 'RB', 'RC', 'RS', 'RT']
26 def __init__(self
, lst
):
28 self
.trans
= self
.translate(lst
)
31 for insn
in self
.trans
:
34 def translate(self
, lst
):
35 isa
= ISA() # reads the v3.0B pseudo-code markdown files
38 # find first space, to get opcode
41 # now find opcode fields
42 fields
= ''.join(ls
[1:]).split(',')
43 fields
= list(map(str.strip
, fields
))
44 print (opcode
, fields
)
46 # identify if is a svp64 mnemonic
47 if not opcode
.startswith('sv.'):
48 res
.append(insn
) # unaltered
51 # start working on decoding the svp64 op: sv.baseop.vec2.mode
52 opmodes
= opcode
.split(".")[1:] # strip leading "sv."
53 v30b_op
= opmodes
.pop(0) # first is the v3.0B
54 if v30b_op
not in isa
.instr
:
55 raise Exception("opcode %s of '%s' not supported" % \
60 if __name__
== '__main__':
61 isa
= SVP64(['slw 3, 1, 4',