move svp64 reg-decode function to more appropriate location
[soc.git] / src / soc / sv / trans / svp64.py
1 # SPDX-License-Identifier: LGPLv3+
2 # Copyright (C) 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Funded by NLnet http://nlnet.nl
4
5 """SVP64 OpenPOWER v3.0B assembly translator
6
7 This class takes raw svp64 assembly mnemonics (aliases excluded) and
8 creates an EXT001-encoded "svp64 prefix" followed by a v3.0B opcode.
9
10 It is very simple and straightforward, the only weirdness being the
11 extraction of the register information and conversion to v3.0B numbering.
12
13 Encoding format of svp64: https://libre-soc.org/openpower/sv/svp64/
14 Bugtracker: https://bugs.libre-soc.org/show_bug.cgi?id=578
15 """
16
17 import os, sys
18 from collections import OrderedDict
19
20 from soc.decoder.pseudo.pagereader import ISA
21 from soc.decoder.power_svp64 import SVP64RM, get_regtype, decode_extra
22
23
24 # decode GPR into sv extra
25 def get_extra_gpr(etype, regmode, field):
26 if regmode == 'scalar':
27 # cut into 2-bits 5-bits SS FFFFF
28 sv_extra = field >> 5
29 field = field & 0b11111
30 else:
31 # cut into 5-bits 2-bits FFFFF SS
32 sv_extra = field & 0b11
33 field = field >> 2
34 return sv_extra, field
35
36
37 # decode 3-bit CR into sv extra
38 def get_extra_cr_3bit(etype, regmode, field):
39 if regmode == 'scalar':
40 # cut into 2-bits 3-bits SS FFF
41 sv_extra = field >> 3
42 field = field & 0b111
43 else:
44 # cut into 3-bits 4-bits FFF SSSS but will cut 2 zeros off later
45 sv_extra = field & 0b1111
46 field = field >> 4
47 return sv_extra, field
48
49
50 # decodes SUBVL
51 def decode_subvl(encoding):
52 pmap = {'2': 0b01, '3': 0b10, '4': 0b11}
53 assert encoding in pmap, \
54 "encoding %s for SUBVL not recognised" % encoding
55 return pmap[encoding]
56
57
58 # decodes elwidth
59 def decode_elwidth(encoding):
60 pmap = {'8': 0b11, '16': 0b10, '32': 0b01}
61 assert encoding in pmap, \
62 "encoding %s for elwidth not recognised" % encoding
63 return pmap[encoding]
64
65
66 # decodes predicate register encoding
67 def decode_predicate(encoding):
68 pmap = { # integer
69 '1<<r3': (0, 0b001),
70 'r3' : (0, 0b010),
71 '~r3' : (0, 0b011),
72 'r10' : (0, 0b100),
73 '~r10' : (0, 0b101),
74 'r30' : (0, 0b110),
75 '~r30' : (0, 0b111),
76 # CR
77 'lt' : (1, 0b000),
78 'nl' : (1, 0b001), 'ge' : (1, 0b001), # same value
79 'gt' : (1, 0b010),
80 'ng' : (1, 0b011), 'le' : (1, 0b011), # same value
81 'eq' : (1, 0b100),
82 'ne' : (1, 0b101),
83 'so' : (1, 0b110), 'un' : (1, 0b110), # same value
84 'ns' : (1, 0b111), 'nu' : (1, 0b111), # same value
85 }
86 assert encoding in pmap, \
87 "encoding %s for predicate not recognised" % encoding
88 return pmap[encoding]
89
90
91 # decodes "Mode" in similar way to BO field (supposed to, anyway)
92 def decode_bo(encoding):
93 pmap = { # TODO: double-check that these are the same as Branch BO
94 'lt' : 0b000,
95 'nl' : 0b001, 'ge' : 0b001, # same value
96 'gt' : 0b010,
97 'ng' : 0b011, 'le' : 0b011, # same value
98 'eq' : 0b100,
99 'ne' : 0b101,
100 'so' : 0b110, 'un' : 0b110, # same value
101 'ns' : 0b111, 'nu' : 0b111, # same value
102 }
103 assert encoding in pmap, \
104 "encoding %s for BO Mode not recognised" % encoding
105 return pmap[encoding]
106
107 # partial-decode fail-first mode
108 def decode_ffirst(encoding):
109 if encoding in ['RC1', '~RC1']:
110 return encoding
111 return decode_bo(encoding)
112
113
114 # decodes svp64 assembly listings and creates EXT001 svp64 prefixes
115 class SVP64:
116 def __init__(self, lst):
117 self.lst = lst
118 self.trans = self.translate(lst)
119
120 def __iter__(self):
121 for insn in self.trans:
122 yield insn
123
124 def translate(self, lst):
125 isa = ISA() # reads the v3.0B pseudo-code markdown files
126 svp64 = SVP64RM() # reads the svp64 Remap entries for registers
127 res = []
128 for insn in lst:
129 # find first space, to get opcode
130 ls = insn.split(' ')
131 opcode = ls[0]
132 # now find opcode fields
133 fields = ''.join(ls[1:]).split(',')
134 fields = list(map(str.strip, fields))
135 print ("opcode, fields", ls, opcode, fields)
136
137 # identify if is a svp64 mnemonic
138 if not opcode.startswith('sv.'):
139 res.append(insn) # unaltered
140 continue
141 opcode = opcode[3:] # strip leading "sv."
142
143 # start working on decoding the svp64 op: sv.basev30Bop/vec2/mode
144 opmodes = opcode.split("/") # split at "/"
145 v30b_op = opmodes.pop(0) # first is the v3.0B
146 # check instruction ends with dot
147 rc_mode = v30b_op.endswith('.')
148 if rc_mode:
149 v30b_op = v30b_op[:-1]
150
151 if v30b_op not in isa.instr:
152 raise Exception("opcode %s of '%s' not supported" % \
153 (v30b_op, insn))
154 if v30b_op not in svp64.instrs:
155 raise Exception("opcode %s of '%s' not an svp64 instruction" % \
156 (v30b_op, insn))
157 v30b_regs = isa.instr[v30b_op].regs[0] # get regs info "RT, RA, RB"
158 rm = svp64.instrs[v30b_op] # one row of the svp64 RM CSV
159 print ("v3.0B op", v30b_op, "Rc=1" if rc_mode else '')
160 print ("v3.0B regs", opcode, v30b_regs)
161 print (rm)
162
163 # right. the first thing to do is identify the ordering of
164 # the registers, by name. the EXTRA2/3 ordering is in
165 # rm['0']..rm['3'] but those fields contain the names RA, BB
166 # etc. we have to read the pseudocode to understand which
167 # reg is which in our instruction. sigh.
168
169 # first turn the svp64 rm into a "by name" dict, recording
170 # which position in the RM EXTRA it goes into
171 # also: record if the src or dest was a CR, for sanity-checking
172 # (elwidth overrides on CRs are banned)
173 decode = decode_extra(rm)
174 dest_reg_cr, src_reg_cr, svp64_src, svp64_dest = decode
175 svp64_reg_byname = {}
176 svp64_reg_byname.update(svp64_src)
177 svp64_reg_byname.update(svp64_dest)
178
179 print ("EXTRA field index, by regname", svp64_reg_byname)
180
181 # okaaay now we identify the field value (opcode N,N,N) with
182 # the pseudo-code info (opcode RT, RA, RB)
183 assert len(fields) == len(v30b_regs), \
184 "length of fields %s must match insn `%s`" % \
185 (str(v30b_regs), insn)
186 opregfields = zip(fields, v30b_regs) # err that was easy
187
188 # now for each of those find its place in the EXTRA encoding
189 extras = OrderedDict()
190 for idx, (field, regname) in enumerate(opregfields):
191 extra = svp64_reg_byname.get(regname, None)
192 regtype = get_regtype(regname)
193 extras[extra] = (idx, field, regname, regtype)
194 print (" ", extra, extras[extra])
195
196 # great! got the extra fields in their associated positions:
197 # also we know the register type. now to create the EXTRA encodings
198 etype = rm['Etype'] # Extra type: EXTRA3/EXTRA2
199 ptype = rm['Ptype'] # Predication type: Twin / Single
200 extra_bits = 0
201 v30b_newfields = []
202 for extra_idx, (idx, field, regname, regtype) in extras.items():
203 # is it a field we don't alter/examine? if so just put it
204 # into newfields
205 if regtype is None:
206 v30b_newfields.append(field)
207
208 # first, decode the field number. "5.v" or "3.s" or "9"
209 field = field.split(".")
210 regmode = 'scalar' # default
211 if len(field) == 2:
212 if field[1] == 's':
213 regmode = 'scalar'
214 elif field[1] == 'v':
215 regmode = 'vector'
216 field = int(field[0]) # actual register number
217 print (" ", regmode, field, end=" ")
218
219 # XXX TODO: the following is a bit of a laborious repeated
220 # mess, which could (and should) easily be parameterised.
221
222 # encode SV-GPR field into extra, v3.0field
223 if regtype == 'GPR':
224 sv_extra, field = get_extra_gpr(etype, regmode, field)
225 # now sanity-check. EXTRA3 is ok, EXTRA2 has limits
226 # (and shrink to a single bit if ok)
227 if etype == 'EXTRA2':
228 if regmode == 'scalar':
229 # range is r0-r63 in increments of 1
230 assert (sv_extra >> 1) == 0, \
231 "scalar GPR %s cannot fit into EXTRA2 %s" % \
232 (regname, str(extras[extra_idx]))
233 # all good: encode as scalar
234 sv_extra = sv_extra & 0b01
235 else:
236 # range is r0-r127 in increments of 4
237 assert sv_extra & 0b01 == 0, \
238 "vector field %s cannot fit into EXTRA2 %s" % \
239 (regname, str(extras[extra_idx]))
240 # all good: encode as vector (bit 2 set)
241 sv_extra = 0b10 | (sv_extra >> 1)
242 elif regmode == 'vector':
243 # EXTRA3 vector bit needs marking
244 sv_extra |= 0b100
245
246 # encode SV-CR 3-bit field into extra, v3.0field
247 elif regtype == 'CR_3bit':
248 sv_extra, field = get_extra_cr_3bit(etype, regmode, field)
249 # now sanity-check (and shrink afterwards)
250 if etype == 'EXTRA2':
251 if regmode == 'scalar':
252 # range is CR0-CR15 in increments of 1
253 assert (sv_extra >> 1) == 0, \
254 "scalar CR %s cannot fit into EXTRA2 %s" % \
255 (regname, str(extras[extra_idx]))
256 # all good: encode as scalar
257 sv_extra = sv_extra & 0b01
258 else:
259 # range is CR0-CR127 in increments of 16
260 assert sv_extra & 0b111 == 0, \
261 "vector CR %s cannot fit into EXTRA2 %s" % \
262 (regname, str(extras[extra_idx]))
263 # all good: encode as vector (bit 2 set)
264 sv_extra = 0b10 | (sv_extra >> 3)
265 else:
266 if regmode == 'scalar':
267 # range is CR0-CR31 in increments of 1
268 assert (sv_extra >> 2) == 0, \
269 "scalar CR %s cannot fit into EXTRA2 %s" % \
270 (regname, str(extras[extra_idx]))
271 # all good: encode as scalar
272 sv_extra = sv_extra & 0b11
273 else:
274 # range is CR0-CR127 in increments of 8
275 assert sv_extra & 0b11 == 0, \
276 "vector CR %s cannot fit into EXTRA2 %s" % \
277 (regname, str(extras[extra_idx]))
278 # all good: encode as vector (bit 3 set)
279 sv_extra = 0b100 | (sv_extra >> 2)
280
281 # encode SV-CR 5-bit field into extra, v3.0field
282 # *sigh* this is the same as 3-bit except the 2 LSBs are
283 # passed through
284 elif regtype == 'CR_5bit':
285 cr_subfield = field & 0b11
286 field = field >> 2 # strip bottom 2 bits
287 sv_extra, field = get_extra_cr_3bit(etype, regmode, field)
288 # now sanity-check (and shrink afterwards)
289 if etype == 'EXTRA2':
290 if regmode == 'scalar':
291 # range is CR0-CR15 in increments of 1
292 assert (sv_extra >> 1) == 0, \
293 "scalar CR %s cannot fit into EXTRA2 %s" % \
294 (regname, str(extras[extra_idx]))
295 # all good: encode as scalar
296 sv_extra = sv_extra & 0b01
297 else:
298 # range is CR0-CR127 in increments of 16
299 assert sv_extra & 0b111 == 0, \
300 "vector CR %s cannot fit into EXTRA2 %s" % \
301 (regname, str(extras[extra_idx]))
302 # all good: encode as vector (bit 2 set)
303 sv_extra = 0b10 | (sv_extra >> 3)
304 else:
305 if regmode == 'scalar':
306 # range is CR0-CR31 in increments of 1
307 assert (sv_extra >> 2) == 0, \
308 "scalar CR %s cannot fit into EXTRA2 %s" % \
309 (regname, str(extras[extra_idx]))
310 # all good: encode as scalar
311 sv_extra = sv_extra & 0b11
312 else:
313 # range is CR0-CR127 in increments of 8
314 assert sv_extra & 0b11 == 0, \
315 "vector CR %s cannot fit into EXTRA2 %s" % \
316 (regname, str(extras[extra_idx]))
317 # all good: encode as vector (bit 3 set)
318 sv_extra = 0b100 | (sv_extra >> 2)
319
320 # reconstruct the actual 5-bit CR field
321 field = (field << 2) | cr_subfield
322
323 # capture the extra field info
324 print ("=>", "%5s" % bin(sv_extra), field)
325 extras[extra_idx] = sv_extra
326
327 # append altered field value to v3.0b
328 v30b_newfields.append(str(field))
329
330 print ("new v3.0B fields", v30b_op, v30b_newfields)
331 print ("extras", extras)
332
333 # rright. now we have all the info. start creating SVP64 RM
334 svp64_rm = 0b0
335
336 # begin with EXTRA fields
337 for idx, sv_extra in extras.items():
338 if idx is None: continue
339 # start at bit 10, work up 2/3 times EXTRA idx
340 offs = 2 if etype == 'EXTRA2' else 3 # 2 or 3 bits
341 svp64_rm |= sv_extra << (10+idx*offs)
342
343 # parts of svp64_rm
344 mmode = 0 # bit 0
345 pmask = 0 # bits 1-3
346 destwid = 0 # bits 4-5
347 srcwid = 0 # bits 6-7
348 subvl = 0 # bits 8-9
349 smask = 0 # bits 16-18 but only for twin-predication
350 mode = 0 # bits 19-23
351
352 has_pmask = False
353 has_smask = False
354
355 saturation = None
356 src_zero = 0
357 dst_zero = 0
358 sv_mode = None
359
360 mapreduce = False
361 mapreduce_crm = False
362 mapreduce_svm = False
363
364 predresult = False
365 failfirst = False
366
367 # ok let's start identifying opcode augmentation fields
368 for encmode in opmodes:
369 # predicate mask (dest)
370 if encmode.startswith("m="):
371 pme = encmode
372 pmmode, pmask = decode_predicate(encmode[2:])
373 mmode = pmmode
374 has_pmask = True
375 # predicate mask (src, twin-pred)
376 elif encmode.startswith("sm="):
377 sme = encmode
378 smmode, smask = decode_predicate(encmode[3:])
379 mmode = smmode
380 has_smask = True
381 # vec2/3/4
382 elif encmode.startswith("vec"):
383 subvl = decode_subvl(encmode[3:])
384 # elwidth
385 elif encmode.startswith("ew="):
386 destwid = decode_elwidth(encmode[3:])
387 elif encmode.startswith("sw="):
388 srcwid = decode_elwidth(encmode[3:])
389 # saturation
390 elif encmode == 'sats':
391 assert sv_mode is None
392 saturation = 1
393 sv_mode = 0b10
394 elif encmode == 'satu':
395 assert sv_mode is None
396 sv_mode = 0b10
397 saturation = 0
398 # predicate zeroing
399 elif encmode == 'sz':
400 src_zero = 1
401 elif encmode == 'dz':
402 dst_zero = 1
403 # failfirst
404 elif encmode.startswith("ff="):
405 assert sv_mode is None
406 sv_mode = 0b01
407 failfirst = decode_ffirst(encmode[3:])
408 # predicate-result, interestingly same as fail-first
409 elif encmode.startswith("pr="):
410 assert sv_mode is None
411 sv_mode = 0b11
412 predresult = decode_ffirst(encmode[3:])
413 # map-reduce mode
414 elif encmode == 'mr':
415 assert sv_mode is None
416 sv_mode = 0b00
417 mapreduce = True
418 elif encmode == 'crm': # CR on map-reduce
419 assert sv_mode is None
420 sv_mode = 0b00
421 mapreduce_crm = True
422 elif encmode == 'svm': # sub-vector mode
423 mapreduce_svm = True
424
425 # sanity-check that 2Pred mask is same mode
426 if has_pmask and has_smask:
427 assert smmode == pmmode, \
428 "predicate masks %s and %s must be same reg type" % \
429 (pme, sme)
430
431 # sanity-check that twin-predication mask only specified in 2P mode
432 if ptype == '1P':
433 assert has_smask == False, \
434 "source-mask can only be specified on Twin-predicate ops"
435
436 # construct the mode field, doing sanity-checking along the way
437
438 if mapreduce_svm:
439 assert sv_mode == 0b00, "sub-vector mode in mapreduce only"
440 assert subvl != 0, "sub-vector mode not possible on SUBVL=1"
441
442 if src_zero:
443 assert has_smask, "src zeroing requires a source predicate"
444 if dst_zero:
445 assert has_pmask, "dest zeroing requires a dest predicate"
446
447 # "normal" mode
448 if sv_mode is None:
449 mode |= (src_zero << 3) | (dst_zero << 4) # predicate zeroing
450 sv_mode = 0b00
451
452 # "mapreduce" modes
453 elif sv_mode == 0b00:
454 mode |= (0b1<<2) # sets mapreduce
455 assert dst_zero == 0, "dest-zero not allowed in mapreduce mode"
456 if mapreduce_crm:
457 mode |= (0b1<<4) # sets CRM mode
458 assert rc_mode, "CRM only allowed when Rc=1"
459 # bit of weird encoding to jam zero-pred or SVM mode in.
460 # SVM mode can be enabled only when SUBVL=2/3/4 (vec2/3/4)
461 if subvl == 0:
462 mode |= (src_zero << 3) # predicate src-zeroing
463 elif mapreduce_svm:
464 mode |= (1 << 3) # SVM mode
465
466 # "failfirst" modes
467 elif sv_mode == 0b01:
468 assert dst_zero == 0, "dest-zero not allowed in failfirst mode"
469 if failfirst == 'RC1':
470 mode |= (0b1<<4) # sets RC1 mode
471 mode |= (src_zero << 3) # predicate src-zeroing
472 assert rc_mode==False, "ffirst RC1 only possible when Rc=0"
473 elif failfirst == '~RC1':
474 mode |= (0b1<<4) # sets RC1 mode...
475 mode |= (src_zero << 3) # predicate src-zeroing
476 mode |= (0b1<<2) # ... with inversion
477 assert rc_mode==False, "ffirst RC1 only possible when Rc=0"
478 else:
479 assert src_zero == 0, "src-zero not allowed in ffirst BO"
480 assert rc_mode, "ffirst BO only possible when Rc=1"
481 mode |= (failfirst << 2) # set BO
482
483 # "saturation" modes
484 elif sv_mode == 0b10:
485 mode |= (src_zero << 3) | (dst_zero << 4) # predicate zeroing
486 mode |= (saturation<<2) # sets signed/unsigned saturation
487
488 # "predicate-result" modes. err... code-duplication from ffirst
489 elif sv_mode == 0b11:
490 assert dst_zero == 0, "dest-zero not allowed in predresult mode"
491 if predresult == 'RC1':
492 mode |= (0b1<<4) # sets RC1 mode
493 mode |= (src_zero << 3) # predicate src-zeroing
494 assert rc_mode==False, "pr-mode RC1 only possible when Rc=0"
495 elif predresult == '~RC1':
496 mode |= (0b1<<4) # sets RC1 mode...
497 mode |= (src_zero << 3) # predicate src-zeroing
498 mode |= (0b1<<2) # ... with inversion
499 assert rc_mode==False, "pr-mode RC1 only possible when Rc=0"
500 else:
501 assert src_zero == 0, "src-zero not allowed in pr-mode BO"
502 assert rc_mode, "pr-mode BO only possible when Rc=1"
503 mode |= (predresult << 2) # set BO
504
505 # whewww.... modes all done :)
506 # now put into svp64_rm
507 mode |= sv_mode
508 svp64_rm |= (mode << 19) # mode: bits 19-23
509
510 # put in predicate masks into svp64_rm
511 if ptype == '2P':
512 svp64_rm |= (smask << 16) # source pred: bits 16-18
513 svp64_rm |= (mmode) # mask mode: bit 0
514 svp64_rm |= (pmask << 1) # 1-pred: bits 1-3
515
516 # and subvl
517 svp64_rm += (subvl << 8) # subvl: bits 8-9
518
519 # put in elwidths
520 svp64_rm += (srcwid << 6) # srcwid: bits 6-7
521 svp64_rm += (destwid << 4) # destwid: bits 4-5
522
523 # nice debug printout. (and now for something completely different)
524 # https://youtu.be/u0WOIwlXE9g?t=146
525 print ("svp64_rm", hex(svp64_rm), bin(svp64_rm))
526 print (" mmode 0 :", bin(mmode))
527 print (" pmask 1-3 :", bin(pmask))
528 print (" dstwid 4-5 :", bin(destwid))
529 print (" srcwid 6-7 :", bin(srcwid))
530 print (" subvl 8-9 :", bin(subvl))
531 print (" mode 19-23:", bin(mode))
532 offs = 2 if etype == 'EXTRA2' else 3 # 2 or 3 bits
533 for idx, sv_extra in extras.items():
534 if idx is None: continue
535 start = (10+idx*offs)
536 end = start + offs-1
537 print (" extra%d %2d-%2d:" % (idx, start, end),
538 bin(sv_extra))
539 if ptype == '2P':
540 print (" smask 16-17:", bin(smask))
541 print ()
542
543 return res
544
545 if __name__ == '__main__':
546 isa = SVP64(['slw 3, 1, 4',
547 'extsw 5, 3',
548 'sv.extsw 5, 3',
549 'sv.cmpi 5, 1, 3, 2',
550 'sv.setb 5, 31',
551 'sv.isel 64.v, 3, 2, 65.v',
552 'sv.setb/m=r3/sm=1<<r3 5, 31',
553 'sv.setb/vec2 5, 31',
554 'sv.setb/sw=8/ew=16 5, 31',
555 'sv.extsw./ff=eq 5, 31',
556 'sv.extsw./satu/sz/dz/sm=r3/m=r3 5, 31',
557 'sv.extsw./pr=eq 5.v, 31',
558 ])
559 csvs = SVP64RM()