1 # SPDX-License-Identifier: LGPLv3+
2 # Copyright (C) 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Funded by NLnet http://nlnet.nl
5 """SVP64 OpenPOWER v3.0B assembly translator
7 This class takes raw svp64 assembly mnemonics (aliases excluded) and
8 creates an EXT001-encoded "svp64 prefix" followed by a v3.0B opcode.
10 It is very simple and straightforward, the only weirdness being the
11 extraction of the register information and conversion to v3.0B numbering.
13 Encoding format of svp64: https://libre-soc.org/openpower/sv/svp64/
14 Bugtracker: https://bugs.libre-soc.org/show_bug.cgi?id=578
18 from collections
import OrderedDict
20 from soc
.decoder
.pseudo
.pagereader
import ISA
21 from soc
.decoder
.power_enums
import get_csv
, find_wiki_dir
24 # identifies register by type
25 def is_CR_3bit(regname
):
26 return regname
in ['BF', 'BFA']
28 def is_CR_5bit(regname
):
29 return regname
in ['BA', 'BB', 'BC', 'BI', 'BT']
32 return regname
in ['RA', 'RB', 'RC', 'RS', 'RT']
34 def get_regtype(regname
):
35 if is_CR_3bit(regname
):
37 if is_CR_5bit(regname
):
43 # gets SVP64 ReMap information
48 for fname
in os
.listdir(pth
):
49 if fname
.startswith("RM"):
50 for entry
in get_csv(fname
):
51 self
.instrs
[entry
['insn']] = entry
54 # decodes svp64 assembly listings and creates EXT001 svp64 prefixes
56 def __init__(self
, lst
):
58 self
.trans
= self
.translate(lst
)
61 for insn
in self
.trans
:
64 def translate(self
, lst
):
65 isa
= ISA() # reads the v3.0B pseudo-code markdown files
66 svp64
= SVP64RM() # reads the svp64 Remap entries for registers
69 # find first space, to get opcode
72 # now find opcode fields
73 fields
= ''.join(ls
[1:]).split(',')
74 fields
= list(map(str.strip
, fields
))
75 print (opcode
, fields
)
77 # identify if is a svp64 mnemonic
78 if not opcode
.startswith('sv.'):
79 res
.append(insn
) # unaltered
82 # start working on decoding the svp64 op: sv.baseop.vec2.mode
83 opmodes
= opcode
.split(".")[1:] # strip leading "sv."
84 v30b_op
= opmodes
.pop(0) # first is the v3.0B
85 if v30b_op
not in isa
.instr
:
86 raise Exception("opcode %s of '%s' not supported" % \
88 if v30b_op
not in svp64
.instrs
:
89 raise Exception("opcode %s of '%s' not an svp64 instruction" % \
91 isa
.instr
[v30b_op
].regs
[0]
92 v30b_regs
= isa
.instr
[v30b_op
].regs
[0]
93 rm
= svp64
.instrs
[v30b_op
]
94 print ("v3.0B regs", opcode
, v30b_regs
)
97 # right. the first thing to do is identify the ordering of
98 # the registers, by name. the EXTRA2/3 ordering is in
99 # rm['0']..rm['3'] but those fields contain the names RA, BB
100 # etc. we have to read the pseudocode to understand which
101 # reg is which in our instruction. sigh.
103 # first turn the svp64 rm into a "by name" dict, recording
104 # which position in the RM EXTRA it goes into
105 svp64_reg_byname
= {}
108 if not rfield
or rfield
== '0':
110 print ("EXTRA field", i
, rfield
)
111 rfield
= rfield
.split(";") # s:RA;d:CR1 etc.
113 r
= r
[2:] # ignore s: and d:
114 svp64_reg_byname
[r
] = i
# this reg in EXTRA position 0-3
115 print ("EXTRA field index, by regname", svp64_reg_byname
)
117 # okaaay now we identify the field value (opcode N,N,N) with
118 # the pseudo-code info (opcode RT, RA, RB)
119 opregfields
= zip(fields
, v30b_regs
) # err that was easy
121 # now for each of those find its place in the EXTRA encoding
122 extras
= OrderedDict()
123 for idx
, (field
, regname
) in enumerate(opregfields
):
124 extra
= svp64_reg_byname
.get(regname
, None)
125 regtype
= get_regtype(regname
)
126 extras
[extra
] = (idx
, field
, regname
, regtype
)
127 print (" ", extra
, extras
[extra
])
129 # great! got the extra fields in their associated positions:
130 # also we know the register type. now to create the EXTRA encodings
131 etype
= rm
['Etype'] # Extra type: EXTRA3/EXTRA2
134 for extra_idx
, (idx
, field
, regname
, regtype
) in extras
.items():
135 # is it a field we don't alter/examine? if so just put it
138 v30b_newfields
.append(field
)
140 # first, decode the field number. "5.v" or "3.s" or "9"
141 field
= field
.split(".")
142 regmode
= 'scalar' # default
146 elif field
[1] == 'v':
148 field
= int(field
[0]) # actual register number
149 print (" ", regmode
, field
)
151 if regmode
== 'scalar':
152 # cut into 2-bits 5-bits SS FFFFF
153 sv_extra
= field
>> 5
154 field
= field
& 0b11111
156 # cut into 5-bits 2-bits FFFFF SS
157 sv_extra
= field
& 0b11
159 # now sanity-check. EXTRA3 is ok, EXTRA2 has limits
160 if etype
== 'EXTRA2':
161 if regmode
== 'scalar':
162 assert sv_extra
& 0b10 == 0, \
163 "scalar field %s cannot fit into EXTRA2 %s" % \
164 (regname
, str(extras
[extra_idx
]))
166 assert sv_extra
& 0b01 == 0, \
167 "vector field %s cannot fit into EXTRA2 %s" % \
168 (regname
, str(extras
[extra_idx
]))
170 # append altered field value to v3.0b
171 v30b_newfields
.append(str(field
))
173 print ("new v3.0B fields", v30b_op
, v30b_newfields
)
178 if __name__
== '__main__':
179 isa
= SVP64(['slw 3, 1, 4',
182 'sv.cmpi 5, 1, 3, 2',
184 'sv.isel 64.v, 3, 2, 0'