src/soc/sv/trans/svp64.py

   1 # SPDX-License-Identifier: LGPLv3+
   2 # Copyright (C) 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   3 # Funded by NLnet http://nlnet.nl
   4
   5 """SVP64 OpenPOWER v3.0B assembly translator
   6
   7 This class takes raw svp64 assembly mnemonics (aliases excluded) and
   8 creates an EXT001-encoded "svp64 prefix" followed by a v3.0B opcode.
   9
  10 It is very simple and straightforward, the only weirdness being the
  11 extraction of the register information and conversion to v3.0B numbering.
  12
  13 Encoding format of svp64: https://libre-soc.org/openpower/sv/svp64/
  14 Bugtracker: https://bugs.libre-soc.org/show_bug.cgi?id=578
  15 """
  16
  17 import os, sys
  18 from collections import OrderedDict
  19
  20 from soc.decoder.pseudo.pagereader import ISA
  21 from soc.decoder.power_enums import get_csv, find_wiki_dir
  22
  23
  24 # identifies register by type
  25 def is_CR_3bit(regname):
  26     return regname in ['BF', 'BFA']
  27
  28 def is_CR_5bit(regname):
  29     return regname in ['BA', 'BB', 'BC', 'BI', 'BT']
  30
  31 def is_GPR(regname):
  32     return regname in ['RA', 'RB', 'RC', 'RS', 'RT']
  33
  34 def get_regtype(regname):
  35     if is_CR_3bit(regname):
  36         return "CR_3bit"
  37     if is_CR_5bit(regname):
  38         return "CR_5bit"
  39     if is_GPR(regname):
  40         return "GPR"
  41
  42 # decode GPR into sv extra
  43 def  get_extra_gpr(etype, regmode, field):
  44     if regmode == 'scalar':
  45         # cut into 2-bits 5-bits SS FFFFF
  46         sv_extra = field >> 5
  47         field = field & 0b11111
  48     else:
  49         # cut into 5-bits 2-bits FFFFF SS
  50         sv_extra = field & 0b11
  51         field = field >> 2
  52     return sv_extra, field
  53
  54
  55 # decode 3-bit CR into sv extra
  56 def  get_extra_cr_3bit(etype, regmode, field):
  57     if regmode == 'scalar':
  58         # cut into 2-bits 3-bits SS FFF
  59         sv_extra = field >> 3
  60         field = field & 0b111
  61     else:
  62         # cut into 3-bits 4-bits FFF SSSS but will cut 2 zeros off later
  63         sv_extra = field & 0b1111
  64         field = field >> 4
  65     return sv_extra, field
  66
  67 # decodes predicate register encoding
  68 def decode_predicate(encoding):
  69     pmap = { # integer
  70             '1<<r3': (0, 0b001),
  71             'r3'   : (0, 0b010),
  72             '~r3'   : (0, 0b011),
  73             'r10'   : (0, 0b100),
  74             '~r10'  : (0, 0b101),
  75             'r30'   : (0, 0b110),
  76             '~r30'  : (0, 0b111),
  77             # CR
  78             'lt'    : (1, 0b000),
  79             'nl'    : (1, 0b001), 'ge'    : (1, 0b001), # same value
  80             'gt'    : (1, 0b010),
  81             'ng'    : (1, 0b011), 'le'    : (1, 0b011), # same value
  82             'eq'    : (1, 0b100),
  83             'ne'    : (1, 0b101),
  84             'so'    : (1, 0b110), 'un'    : (1, 0b110), # same value
  85             'ns'    : (1, 0b111), 'nu'    : (1, 0b111), # same value
  86            }
  87     assert encoding in pmap, \
  88         "encoding %s for predicate not recognised" % encoding
  89     return pmap[encoding]
  90
  91
  92 # gets SVP64 ReMap information
  93 class SVP64RM:
  94     def __init__(self):
  95         self.instrs = {}
  96         pth = find_wiki_dir()
  97         for fname in os.listdir(pth):
  98             if fname.startswith("RM"):
  99                 for entry in get_csv(fname):
 100                     self.instrs[entry['insn']] = entry
 101
 102
 103 # decodes svp64 assembly listings and creates EXT001 svp64 prefixes
 104 class SVP64:
 105     def __init__(self, lst):
 106         self.lst = lst
 107         self.trans = self.translate(lst)
 108
 109     def __iter__(self):
 110         for insn in self.trans:
 111             yield insn
 112
 113     def translate(self, lst):
 114         isa = ISA() # reads the v3.0B pseudo-code markdown files
 115         svp64 = SVP64RM() # reads the svp64 Remap entries for registers
 116         res = []
 117         for insn in lst:
 118             # find first space, to get opcode
 119             ls = insn.split(' ')
 120             opcode = ls[0]
 121             # now find opcode fields
 122             fields = ''.join(ls[1:]).split(',')
 123             fields = list(map(str.strip, fields))
 124             print ("opcode, fields", ls, opcode, fields)
 125
 126             # identify if is a svp64 mnemonic
 127             if not opcode.startswith('sv.'):
 128                 res.append(insn) # unaltered
 129                 continue
 130
 131             # start working on decoding the svp64 op: sv.baseop.vec2.mode
 132             opmodes = opcode.split(".")[1:] # strip leading "sv."
 133             v30b_op = opmodes.pop(0)        # first is the v3.0B
 134             if v30b_op not in isa.instr:
 135                 raise Exception("opcode %s of '%s' not supported" % \
 136                                 (v30b_op, insn))
 137             if v30b_op not in svp64.instrs:
 138                 raise Exception("opcode %s of '%s' not an svp64 instruction" % \
 139                                 (v30b_op, insn))
 140             isa.instr[v30b_op].regs[0]
 141             v30b_regs = isa.instr[v30b_op].regs[0]
 142             rm = svp64.instrs[v30b_op]
 143             print ("v3.0B regs", opcode, v30b_regs)
 144             print (rm)
 145
 146             # right.  the first thing to do is identify the ordering of
 147             # the registers, by name.  the EXTRA2/3 ordering is in
 148             # rm['0']..rm['3'] but those fields contain the names RA, BB
 149             # etc.  we have to read the pseudocode to understand which
 150             # reg is which in our instruction. sigh.
 151
 152             # first turn the svp64 rm into a "by name" dict, recording
 153             # which position in the RM EXTRA it goes into
 154             svp64_reg_byname = {}
 155             for i in range(4):
 156                 rfield = rm[str(i)]
 157                 if not rfield or rfield == '0':
 158                     continue
 159                 print ("EXTRA field", i, rfield)
 160                 rfield = rfield.split(";") # s:RA;d:CR1 etc.
 161                 for r in rfield:
 162                     r = r[2:] # ignore s: and d:
 163                     svp64_reg_byname[r] = i # this reg in EXTRA position 0-3
 164             print ("EXTRA field index, by regname", svp64_reg_byname)
 165
 166             # okaaay now we identify the field value (opcode N,N,N) with
 167             # the pseudo-code info (opcode RT, RA, RB)
 168             opregfields = zip(fields, v30b_regs) # err that was easy
 169
 170             # now for each of those find its place in the EXTRA encoding
 171             extras = OrderedDict()
 172             for idx, (field, regname) in enumerate(opregfields):
 173                 extra = svp64_reg_byname.get(regname, None)
 174                 regtype = get_regtype(regname)
 175                 extras[extra] = (idx, field, regname, regtype)
 176                 print ("    ", extra, extras[extra])
 177
 178             # great! got the extra fields in their associated positions:
 179             # also we know the register type. now to create the EXTRA encodings
 180             etype = rm['Etype'] # Extra type: EXTRA3/EXTRA2
 181             ptype = rm['Ptype'] # Predication type: Twin / Single
 182             extra_bits = 0
 183             v30b_newfields = []
 184             for extra_idx, (idx, field, regname, regtype) in extras.items():
 185                 # is it a field we don't alter/examine?  if so just put it
 186                 # into newfields
 187                 if regtype is None:
 188                     v30b_newfields.append(field)
 189
 190                 # first, decode the field number. "5.v" or "3.s" or "9"
 191                 field = field.split(".")
 192                 regmode = 'scalar' # default
 193                 if len(field) == 2:
 194                     if field[1] == 's':
 195                         regmode = 'scalar'
 196                     elif field[1] == 'v':
 197                         regmode = 'vector'
 198                 field = int(field[0]) # actual register number
 199                 print ("    ", regmode, field, end=" ")
 200
 201                 # XXX TODO: the following is a bit of a laborious repeated
 202                 # mess, which could (and should) easily be parameterised.
 203
 204                 # encode SV-GPR field into extra, v3.0field
 205                 if regtype == 'GPR':
 206                     sv_extra, field = get_extra_gpr(etype, regmode, field)
 207                     # now sanity-check. EXTRA3 is ok, EXTRA2 has limits
 208                     # (and shrink to a single bit if ok)
 209                     if etype == 'EXTRA2':
 210                         if regmode == 'scalar':
 211                             # range is r0-r63 in increments of 1
 212                             assert (sv_extra >> 1) == 0, \
 213                                 "scalar GPR %s cannot fit into EXTRA2 %s" % \
 214                                     (regname, str(extras[extra_idx]))
 215                             # all good: encode as scalar
 216                             sv_extra = sv_extra & 0b01
 217                         else:
 218                             # range is r0-r127 in increments of 4
 219                             assert sv_extra & 0b01 == 0, \
 220                                 "vector field %s cannot fit into EXTRA2 %s" % \
 221                                     (regname, str(extras[extra_idx]))
 222                             # all good: encode as vector (bit 2 set)
 223                             sv_extra = 0b10 | (sv_extra >> 1)
 224                     elif regmode == 'vector':
 225                         # EXTRA3 vector bit needs marking
 226                         sv_extra |= 0b100
 227
 228                 # encode SV-CR 3-bit field into extra, v3.0field
 229                 elif regtype == 'CR_3bit':
 230                     sv_extra, field = get_extra_cr_3bit(etype, regmode, field)
 231                     # now sanity-check (and shrink afterwards)
 232                     if etype == 'EXTRA2':
 233                         if regmode == 'scalar':
 234                             # range is CR0-CR15 in increments of 1
 235                             assert (sv_extra >> 1) == 0, \
 236                                 "scalar CR %s cannot fit into EXTRA2 %s" % \
 237                                     (regname, str(extras[extra_idx]))
 238                             # all good: encode as scalar
 239                             sv_extra = sv_extra & 0b01
 240                         else:
 241                             # range is CR0-CR127 in increments of 16
 242                             assert sv_extra & 0b111 == 0, \
 243                                 "vector CR %s cannot fit into EXTRA2 %s" % \
 244                                     (regname, str(extras[extra_idx]))
 245                             # all good: encode as vector (bit 2 set)
 246                             sv_extra = 0b10 | (sv_extra >> 3)
 247                     else:
 248                         if regmode == 'scalar':
 249                             # range is CR0-CR31 in increments of 1
 250                             assert (sv_extra >> 2) == 0, \
 251                                 "scalar CR %s cannot fit into EXTRA2 %s" % \
 252                                     (regname, str(extras[extra_idx]))
 253                             # all good: encode as scalar
 254                             sv_extra = sv_extra & 0b11
 255                         else:
 256                             # range is CR0-CR127 in increments of 8
 257                             assert sv_extra & 0b11 == 0, \
 258                                 "vector CR %s cannot fit into EXTRA2 %s" % \
 259                                     (regname, str(extras[extra_idx]))
 260                             # all good: encode as vector (bit 3 set)
 261                             sv_extra = 0b100 | (sv_extra >> 2)
 262
 263                 # encode SV-CR 5-bit field into extra, v3.0field
 264                 # *sigh* this is the same as 3-bit except the 2 LSBs are
 265                 # passed through
 266                 elif regtype == 'CR_5bit':
 267                     cr_subfield = field & 0b11
 268                     field = field >> 2 # strip bottom 2 bits
 269                     sv_extra, field = get_extra_cr_3bit(etype, regmode, field)
 270                     # now sanity-check (and shrink afterwards)
 271                     if etype == 'EXTRA2':
 272                         if regmode == 'scalar':
 273                             # range is CR0-CR15 in increments of 1
 274                             assert (sv_extra >> 1) == 0, \
 275                                 "scalar CR %s cannot fit into EXTRA2 %s" % \
 276                                     (regname, str(extras[extra_idx]))
 277                             # all good: encode as scalar
 278                             sv_extra = sv_extra & 0b01
 279                         else:
 280                             # range is CR0-CR127 in increments of 16
 281                             assert sv_extra & 0b111 == 0, \
 282                                 "vector CR %s cannot fit into EXTRA2 %s" % \
 283                                     (regname, str(extras[extra_idx]))
 284                             # all good: encode as vector (bit 2 set)
 285                             sv_extra = 0b10 | (sv_extra >> 3)
 286                     else:
 287                         if regmode == 'scalar':
 288                             # range is CR0-CR31 in increments of 1
 289                             assert (sv_extra >> 2) == 0, \
 290                                 "scalar CR %s cannot fit into EXTRA2 %s" % \
 291                                     (regname, str(extras[extra_idx]))
 292                             # all good: encode as scalar
 293                             sv_extra = sv_extra & 0b11
 294                         else:
 295                             # range is CR0-CR127 in increments of 8
 296                             assert sv_extra & 0b11 == 0, \
 297                                 "vector CR %s cannot fit into EXTRA2 %s" % \
 298                                     (regname, str(extras[extra_idx]))
 299                             # all good: encode as vector (bit 3 set)
 300                             sv_extra = 0b100 | (sv_extra >> 2)
 301
 302                     # reconstruct the actual 5-bit CR field
 303                     field = (field << 2) | cr_subfield
 304
 305                 # capture the extra field info
 306                 print ("=>", "%5s" % bin(sv_extra), field)
 307                 extras[extra_idx] = sv_extra
 308
 309                 # append altered field value to v3.0b
 310                 v30b_newfields.append(str(field))
 311
 312             print ("new v3.0B fields", v30b_op, v30b_newfields)
 313             print ("extras", extras)
 314
 315             # rright.  now we have all the info. start creating SVP64 RM
 316             svp64_rm = 0b0
 317
 318             # begin with EXTRA fields
 319             for idx, sv_extra in extras.items():
 320                 if idx is None: continue
 321                 # start at bit 10, work up 2/3 times EXTRA idx
 322                 offs = 2 if etype == 'EXTRA2' else 3 # 2 or 3 bits
 323                 svp64_rm |= sv_extra << (10+idx*offs)
 324
 325             # parts of svp64_rm
 326             mmode = 0  # bit 0
 327             pmask = 0  # bits 1-3
 328             destwid = 0 # bits 4-5
 329             srcwid = 0 # bits 6-7
 330             subvl = 0   # bits 8-9
 331             smask = 0 # bits 16-18 but only for twin-predication
 332             mode = 0 # bits 19-23
 333
 334             has_pmask = False
 335             has_smask = False
 336
 337             # ok let's start identifying opcode augmentation fields
 338             for encmode in opmodes:
 339                 # predicate mask (dest)
 340                 if encmode.startswith("m="):
 341                     pme = encmode
 342                     pmmode, pmask = decode_predicate(encmode[2:])
 343                     mmode = pmmode
 344                     has_pmask = True
 345                 # predicate mask (src, twin-pred)
 346                 if encmode.startswith("sm="):
 347                     sme = encmode
 348                     smmode, smask = decode_predicate(encmode[2:])
 349                     mmode = smmode
 350                     has_smask = True
 351
 352             # sanity-check that 2Pred mask is same mode
 353             if has_pmask and has_smask:
 354                 assert smmode == pmmode, \
 355                     "predicate masks %s and %s must be same reg type" % \
 356                         (pme, sme)
 357
 358             # sanity-check that twin-predication mask only specified in 2P mode
 359             if ptype == '1P':
 360                 assert has_smask == False, \
 361                     "source-mask can only be specified on Twin-predicate ops"
 362
 363             # put in predicate masks into svp64_rm
 364             if ptype == '2P':
 365                 svp64_rm |= (smask << 16) # source pred: bits 16-18
 366             svp64_rm |= (mmode)           # mask mode: bit 0
 367             svp64_rm |= (pmask << 1)      # 1-pred: bits 1-3
 368
 369             print ("svp64_rm", hex(svp64_rm), bin(svp64_rm))
 370             print ()
 371
 372         return res
 373
 374 if __name__ == '__main__':
 375     isa = SVP64(['slw 3, 1, 4',
 376                  'extsw 5, 3',
 377                  'sv.extsw 5, 3',
 378                  'sv.cmpi 5, 1, 3, 2',
 379                  'sv.setb 5, 31',
 380                  'sv.isel 64.v, 3, 2, 65.v',
 381                  'sv.setb.m=r3 5, 31',
 382                 ])
 383     csvs = SVP64RM()