src/unused/TLB/ariane/test/test_ptw.py

   1 from nmigen.compat.sim import run_simulation
   2 from soc.TLB.ariane.ptw import PTW, PTE
   3
   4 # unit was changed, test needs to be changed
   5
   6
   7 def tbench(dut):
   8
   9     addr = 0x8000000
  10
  11     #pte = PTE()
  12     # yield pte.v.eq(1)
  13     # yield pte.r.eq(1)
  14
  15     yield dut.req_port_i.data_gnt.eq(1)
  16     yield dut.req_port_i.data_rvalid.eq(1)
  17     yield dut.req_port_i.data_rdata.eq(0x43)  # pte.flatten())
  18
  19     # data lookup
  20     yield dut.en_ld_st_translation_i.eq(1)
  21     yield dut.asid_i.eq(1)
  22
  23     yield dut.dtlb_access_i.eq(1)
  24     yield dut.dtlb_hit_i.eq(0)
  25     yield dut.dtlb_vaddr_i.eq(0x400000000)
  26
  27     yield
  28     yield
  29     yield
  30
  31     yield dut.dtlb_access_i.eq(1)
  32     yield dut.dtlb_hit_i.eq(0)
  33     yield dut.dtlb_vaddr_i.eq(0x200000)
  34
  35     yield
  36     yield
  37     yield
  38
  39     yield dut.req_port_i.data_gnt.eq(0)
  40     yield dut.dtlb_access_i.eq(1)
  41     yield dut.dtlb_hit_i.eq(0)
  42     yield dut.dtlb_vaddr_i.eq(0x400000011)
  43
  44     yield
  45     yield dut.req_port_i.data_gnt.eq(1)
  46     yield
  47     yield
  48
  49     # data lookup, PTW levels 1-2-3
  50     addr = 0x4000000
  51     yield dut.dtlb_vaddr_i.eq(addr)
  52     yield dut.mxr_i.eq(0x1)
  53     yield dut.req_port_i.data_gnt.eq(1)
  54     yield dut.req_port_i.data_rvalid.eq(1)
  55     # pte.flatten())
  56     yield dut.req_port_i.data_rdata.eq(0x41 | (addr >> 12) << 10)
  57
  58     yield dut.en_ld_st_translation_i.eq(1)
  59     yield dut.asid_i.eq(1)
  60
  61     yield dut.dtlb_access_i.eq(1)
  62     yield dut.dtlb_hit_i.eq(0)
  63     yield dut.dtlb_vaddr_i.eq(addr)
  64
  65     yield
  66     yield
  67     yield
  68     yield
  69     yield
  70     yield
  71     yield
  72     yield
  73
  74     yield dut.req_port_i.data_gnt.eq(0)
  75     yield dut.dtlb_access_i.eq(1)
  76     yield dut.dtlb_hit_i.eq(0)
  77     yield dut.dtlb_vaddr_i.eq(0x400000011)
  78
  79     yield
  80     yield dut.req_port_i.data_gnt.eq(1)
  81     yield
  82     yield
  83     yield
  84     yield
  85
  86     # instruction lookup
  87     yield dut.en_ld_st_translation_i.eq(0)
  88     yield dut.enable_translation_i.eq(1)
  89     yield dut.asid_i.eq(1)
  90
  91     yield dut.itlb_access_i.eq(1)
  92     yield dut.itlb_hit_i.eq(0)
  93     yield dut.itlb_vaddr_i.eq(0x800000)
  94
  95     yield
  96     yield
  97     yield
  98
  99     yield dut.itlb_access_i.eq(1)
 100     yield dut.itlb_hit_i.eq(0)
 101     yield dut.itlb_vaddr_i.eq(0x200000)
 102
 103     yield
 104     yield
 105     yield
 106
 107     yield dut.req_port_i.data_gnt.eq(0)
 108     yield dut.itlb_access_i.eq(1)
 109     yield dut.itlb_hit_i.eq(0)
 110     yield dut.itlb_vaddr_i.eq(0x800011)
 111
 112     yield
 113     yield dut.req_port_i.data_gnt.eq(1)
 114     yield
 115     yield
 116
 117     yield
 118
 119
 120 def test_ptw():
 121     dut = PTW()
 122     run_simulation(dut, tbench(dut), vcd_name="test_ptw.vcd")
 123     print("PTW Unit Test Success")
 124
 125
 126 if __name__ == "__main__":
 127     test_ptw()