1 from nmigen
.compat
.sim
import run_simulation
3 from soc
.TLB
.ariane
.tlb_content
import TLBContent
4 from soc
.TestUtil
.test_helper
import assert_op
, assert_eq
7 def update(dut
, a
, t
, g
, m
):
8 yield dut
.replace_en_i
.eq(1)
9 yield dut
.update_i
.valid
.eq(1)
10 yield dut
.update_i
.is_512G
.eq(t
)
11 yield dut
.update_i
.is_1G
.eq(g
)
12 yield dut
.update_i
.is_2M
.eq(m
)
13 yield dut
.update_i
.vpn
.eq(a
)
18 def check_hit(dut
, hit
, pagesize
):
19 hit_d
= yield dut
.lu_hit_o
20 assert_eq("hit", hit_d
, hit
)
24 hitp
= yield dut
.lu_is_512G_o
25 assert_eq("lu_is_512G_o", hitp
, 1)
26 elif(pagesize
== "g"):
27 hitp
= yield dut
.lu_is_1G_o
28 assert_eq("lu_is_1G_o", hitp
, 1)
29 elif(pagesize
== "m"):
30 hitp
= yield dut
.lu_is_2M_o
31 assert_eq("lu_is_2M_o", hitp
, 1)
35 return a | b
<< 9 | c
<< 18 | d
<< 27
39 yield dut
.vpn0
.eq(0x0A)
40 yield dut
.vpn1
.eq(0x0B)
41 yield dut
.vpn2
.eq(0x0C)
42 yield dut
.vpn3
.eq(0x0D)
43 yield from update(dut
, addr(0xFF, 0xFF, 0xFF, 0x0D), 1, 0, 0)
44 yield from check_hit(dut
, 1, "t")
46 yield from update(dut
, addr(0xFF, 0xFF, 0x0C, 0x0D), 0, 1, 0)
47 yield from check_hit(dut
, 1, "g")
49 yield from update(dut
, addr(0xFF, 0x0B, 0x0C, 0x0D), 0, 0, 1)
50 yield from check_hit(dut
, 1, "m")
52 yield from update(dut
, addr(0x0A, 0x0B, 0x0C, 0x0D), 0, 0, 0)
53 yield from check_hit(dut
, 1, "")
55 yield from update(dut
, addr(0xAA, 0xBB, 0xCC, 0xDD), 0, 0, 0)
56 yield from check_hit(dut
, 0, "miss")
59 if __name__
== "__main__":
60 dut
= TLBContent(4, 4)
62 run_simulation(dut
, tbench(dut
), vcd_name
="test_tlb_content.vcd")
63 print("TLBContent Unit Test Success")