src/unused/TLB/test/test_LFSR2.py

   1 # SPDX-License-Identifier: LGPL-2.1-or-later
   2 # See Notices.txt for copyright information
   3 from soc.TLB.LFSR import LFSR, LFSRPolynomial, LFSR_POLY_3
   4
   5 from nmigen.back.pysim import Simulator, Delay, Tick
   6 import unittest
   7
   8
   9 class TestLFSR(unittest.TestCase):
  10     def test_poly(self):
  11         v = LFSRPolynomial()
  12         self.assertEqual(repr(v), "LFSRPolynomial([0])")
  13         self.assertEqual(str(v), "1")
  14         v = LFSRPolynomial([1])
  15         self.assertEqual(repr(v), "LFSRPolynomial([1, 0])")
  16         self.assertEqual(str(v), "x + 1")
  17         v = LFSRPolynomial([0, 1])
  18         self.assertEqual(repr(v), "LFSRPolynomial([1, 0])")
  19         self.assertEqual(str(v), "x + 1")
  20         v = LFSRPolynomial([1, 2])
  21         self.assertEqual(repr(v), "LFSRPolynomial([2, 1, 0])")
  22         self.assertEqual(str(v), "x^2 + x + 1")
  23         v = LFSRPolynomial([2])
  24         self.assertEqual(repr(v), "LFSRPolynomial([2, 0])")
  25         self.assertEqual(str(v), "x^2 + 1")
  26         self.assertEqual(str(LFSR_POLY_3), "x^3 + x^2 + 1")
  27
  28     def test_lfsr_3(self):
  29         module = LFSR(LFSR_POLY_3)
  30         traces = [module.state, module.enable]
  31         with Simulator(module,
  32                        vcd_file=open("Waveforms/test_LFSR2.vcd", "w"),
  33                        gtkw_file=open("Waveforms/test_LFSR2.gtkw", "w"),
  34                        traces=traces) as sim:
  35             sim.add_clock(1e-6, phase=0.25e-6)
  36             delay = Delay(1e-7)
  37
  38             def async_process():
  39                 yield module.enable.eq(0)
  40                 yield Tick()
  41                 self.assertEqual((yield module.state), 0x1)
  42                 yield Tick()
  43                 self.assertEqual((yield module.state), 0x1)
  44                 yield module.enable.eq(1)
  45                 yield Tick()
  46                 yield delay
  47                 self.assertEqual((yield module.state), 0x2)
  48                 yield Tick()
  49                 yield delay
  50                 self.assertEqual((yield module.state), 0x5)
  51                 yield Tick()
  52                 yield delay
  53                 self.assertEqual((yield module.state), 0x3)
  54                 yield Tick()
  55                 yield delay
  56                 self.assertEqual((yield module.state), 0x7)
  57                 yield Tick()
  58                 yield delay
  59                 self.assertEqual((yield module.state), 0x6)
  60                 yield Tick()
  61                 yield delay
  62                 self.assertEqual((yield module.state), 0x4)
  63                 yield Tick()
  64                 yield delay
  65                 self.assertEqual((yield module.state), 0x1)
  66                 yield Tick()
  67
  68             sim.add_process(async_process)
  69             sim.run()