src/unused/TLB/test/test_cam.py

   1 from nmigen.compat.sim import run_simulation
   2
   3 from soc.TLB.Cam import Cam
   4
   5 from soc.TestUtil.test_helper import assert_eq, assert_ne, assert_op
   6
   7 # This function allows for the easy setting of values to the Cam
   8 # Arguments:
   9 #   dut: The Cam being tested
  10 #   e (Enable): Whether the block is going to be enabled
  11 #   we (Write Enable): Whether the Cam will write on the next cycle
  12 #   a (Address): Where the data will be written if write enable is high
  13 #   d (Data): Either what we are looking for or will write to the address
  14
  15
  16 def set_cam(dut, e, we, a, d):
  17     yield dut.enable.eq(e)
  18     yield dut.write_enable.eq(we)
  19     yield dut.address_in.eq(a)
  20     yield dut.data_in.eq(d)
  21     yield
  22
  23 # Checks the multiple match of the Cam
  24 # Arguments:
  25 #   dut: The Cam being tested
  26 #   mm (Multiple Match): The expected match result
  27 #   op (Operation): (0 => ==), (1 => !=)
  28
  29
  30 def check_multiple_match(dut, mm, op):
  31     out_mm = yield dut.multiple_match
  32     assert_op("Multiple Match", out_mm, mm, op)
  33
  34 # Checks the single match of the Cam
  35 # Arguments:
  36 #   dut: The Cam being tested
  37 #   sm (Single Match): The expected match result
  38 #   op (Operation): (0 => ==), (1 => !=)
  39
  40
  41 def check_single_match(dut, sm, op):
  42     out_sm = yield dut.single_match
  43     assert_op("Single Match", out_sm, sm, op)
  44
  45 # Checks the address output of the Cam
  46 # Arguments:
  47 #   dut: The Cam being tested
  48 #   ma (Match Address): The expected match result
  49 #   op (Operation): (0 => ==), (1 => !=)
  50
  51
  52 def check_match_address(dut, ma, op):
  53     out_ma = yield dut.match_address
  54     assert_op("Match Address", out_ma, ma, op)
  55
  56 # Checks the state of the Cam
  57 # Arguments:
  58 #   dut: The Cam being tested
  59 #   sm (Single Match): The expected match result
  60 #   mm (Multiple Match): The expected match result
  61 #   ma: (Match Address): The expected address output
  62 #   ss_op (Operation): Operation for the match assertion (0 => ==), (1 => !=)
  63 #   mm_op (Operation): Operation for the match assertion (0 => ==), (1 => !=)
  64 #   ma_op (Operation): Operation for the address assertion (0 => ==), (1 => !=)
  65
  66
  67 def check_all(dut, mm, sm, ma, mm_op, sm_op, ma_op):
  68     yield from check_multiple_match(dut, mm, mm_op)
  69     yield from check_single_match(dut, sm, sm_op)
  70     yield from check_match_address(dut, ma, ma_op)
  71
  72
  73 def tbench(dut):
  74     # NA
  75     enable = 0
  76     write_enable = 0
  77     address = 0
  78     data = 0
  79     single_match = 0
  80     yield from set_cam(dut, enable, write_enable, address, data)
  81     yield
  82     yield from check_single_match(dut, single_match, 0)
  83
  84     # Read Miss Multiple
  85     # Note that the default starting entry data bits are all 0
  86     enable = 1
  87     write_enable = 0
  88     address = 0
  89     data = 0
  90     multiple_match = 1
  91     single_match = 0
  92     yield from set_cam(dut, enable, write_enable, address, data)
  93     yield
  94     yield from check_multiple_match(dut, multiple_match, 0)
  95
  96     # Read Miss
  97     # Note that the default starting entry data bits are all 0
  98     enable = 1
  99     write_enable = 0
 100     address = 0
 101     data = 1
 102     multiple_match = 0
 103     single_match = 0
 104     yield from set_cam(dut, enable, write_enable, address, data)
 105     yield
 106     yield from check_single_match(dut, single_match, 0)
 107
 108     # Write Entry 0
 109     enable = 1
 110     write_enable = 1
 111     address = 0
 112     data = 4
 113     multiple_match = 0
 114     single_match = 0
 115     yield from set_cam(dut, enable, write_enable, address, data)
 116     yield
 117     yield from check_single_match(dut, single_match, 0)
 118
 119     # Read Hit Entry 0
 120     enable = 1
 121     write_enable = 0
 122     address = 0
 123     data = 4
 124     multiple_match = 0
 125     single_match = 1
 126     yield from set_cam(dut, enable, write_enable, address, data)
 127     yield
 128     yield from check_all(dut, multiple_match, single_match, address, 0, 0, 0)
 129
 130     # Search Hit
 131     enable = 1
 132     write_enable = 0
 133     address = 0
 134     data = 4
 135     multiple_match = 0
 136     single_match = 1
 137     yield from set_cam(dut, enable, write_enable, address, data)
 138     yield
 139     yield from check_all(dut, multiple_match, single_match, address, 0, 0, 0)
 140
 141     # Search Miss
 142     enable = 1
 143     write_enable = 0
 144     address = 0
 145     data = 5
 146     single_match = 0
 147     yield from set_cam(dut, enable, write_enable, address, data)
 148     yield
 149     yield from check_single_match(dut, single_match, 0)
 150
 151     # Multiple Match test
 152     # Write Entry 1
 153     enable = 1
 154     write_enable = 1
 155     address = 1
 156     data = 5
 157     multiple_match = 0
 158     single_match = 0
 159     yield from set_cam(dut, enable, write_enable, address, data)
 160     yield
 161     yield from check_single_match(dut, single_match, 0)
 162
 163     # Write Entry 2
 164     # Same data as Entry 1
 165     enable = 1
 166     write_enable = 1
 167     address = 2
 168     data = 5
 169     multiple_match = 0
 170     single_match = 0
 171     yield from set_cam(dut, enable, write_enable, address, data)
 172     yield
 173     yield from check_single_match(dut, single_match, 0)
 174
 175     # Read Hit Data 5
 176     enable = 1
 177     write_enable = 0
 178     address = 1
 179     data = 5
 180     multiple_match = 1
 181     single_match = 0
 182     yield from set_cam(dut, enable, write_enable, address, data)
 183     yield
 184     yield from check_all(dut, multiple_match, single_match, address, 0, 0, 0)
 185
 186     # Verify read_warning is not caused
 187     # Write Entry 0
 188     enable = 1
 189     write_enable = 1
 190     address = 0
 191     data = 7
 192     multiple_match = 0
 193     single_match = 0
 194     yield from set_cam(dut, enable, write_enable, address, data)
 195     # Note there is no yield we immediately attempt to read in the next cycle
 196
 197     # Read Hit Data 7
 198     enable = 1
 199     write_enable = 0
 200     address = 0
 201     data = 7
 202     multiple_match = 0
 203     single_match = 1
 204     yield from set_cam(dut, enable, write_enable, address, data)
 205     yield
 206     yield from check_single_match(dut, single_match, 0)
 207
 208     yield
 209
 210
 211 def test_cam():
 212     dut = Cam(4, 4)
 213     run_simulation(dut, tbench(dut), vcd_name="Waveforms/test_cam.vcd")
 214     print("Cam Unit Test Success")
 215
 216
 217 if __name__ == "__main__":
 218     test_cam()