d11cd974f58187669b0c5401c2f15ca9ba1c8a78
1 from nmigen
.compat
.sim
import run_simulation
3 from soc
.TLB
.Cam
import Cam
5 from soc
.TestUtil
.test_helper
import assert_eq
, assert_ne
, assert_op
7 # This function allows for the easy setting of values to the Cam
9 # dut: The Cam being tested
10 # e (Enable): Whether the block is going to be enabled
11 # we (Write Enable): Whether the Cam will write on the next cycle
12 # a (Address): Where the data will be written if write enable is high
13 # d (Data): Either what we are looking for or will write to the address
16 def set_cam(dut
, e
, we
, a
, d
):
17 yield dut
.enable
.eq(e
)
18 yield dut
.write_enable
.eq(we
)
19 yield dut
.address_in
.eq(a
)
20 yield dut
.data_in
.eq(d
)
23 # Checks the multiple match of the Cam
25 # dut: The Cam being tested
26 # mm (Multiple Match): The expected match result
27 # op (Operation): (0 => ==), (1 => !=)
30 def check_multiple_match(dut
, mm
, op
):
31 out_mm
= yield dut
.multiple_match
32 assert_op("Multiple Match", out_mm
, mm
, op
)
34 # Checks the single match of the Cam
36 # dut: The Cam being tested
37 # sm (Single Match): The expected match result
38 # op (Operation): (0 => ==), (1 => !=)
41 def check_single_match(dut
, sm
, op
):
42 out_sm
= yield dut
.single_match
43 assert_op("Single Match", out_sm
, sm
, op
)
45 # Checks the address output of the Cam
47 # dut: The Cam being tested
48 # ma (Match Address): The expected match result
49 # op (Operation): (0 => ==), (1 => !=)
52 def check_match_address(dut
, ma
, op
):
53 out_ma
= yield dut
.match_address
54 assert_op("Match Address", out_ma
, ma
, op
)
56 # Checks the state of the Cam
58 # dut: The Cam being tested
59 # sm (Single Match): The expected match result
60 # mm (Multiple Match): The expected match result
61 # ma: (Match Address): The expected address output
62 # ss_op (Operation): Operation for the match assertion (0 => ==), (1 => !=)
63 # mm_op (Operation): Operation for the match assertion (0 => ==), (1 => !=)
64 # ma_op (Operation): Operation for the address assertion (0 => ==), (1 => !=)
67 def check_all(dut
, mm
, sm
, ma
, mm_op
, sm_op
, ma_op
):
68 yield from check_multiple_match(dut
, mm
, mm_op
)
69 yield from check_single_match(dut
, sm
, sm_op
)
70 yield from check_match_address(dut
, ma
, ma_op
)
80 yield from set_cam(dut
, enable
, write_enable
, address
, data
)
82 yield from check_single_match(dut
, single_match
, 0)
85 # Note that the default starting entry data bits are all 0
92 yield from set_cam(dut
, enable
, write_enable
, address
, data
)
94 yield from check_multiple_match(dut
, multiple_match
, 0)
97 # Note that the default starting entry data bits are all 0
104 yield from set_cam(dut
, enable
, write_enable
, address
, data
)
106 yield from check_single_match(dut
, single_match
, 0)
115 yield from set_cam(dut
, enable
, write_enable
, address
, data
)
117 yield from check_single_match(dut
, single_match
, 0)
126 yield from set_cam(dut
, enable
, write_enable
, address
, data
)
128 yield from check_all(dut
, multiple_match
, single_match
, address
, 0, 0, 0)
137 yield from set_cam(dut
, enable
, write_enable
, address
, data
)
139 yield from check_all(dut
, multiple_match
, single_match
, address
, 0, 0, 0)
147 yield from set_cam(dut
, enable
, write_enable
, address
, data
)
149 yield from check_single_match(dut
, single_match
, 0)
151 # Multiple Match test
159 yield from set_cam(dut
, enable
, write_enable
, address
, data
)
161 yield from check_single_match(dut
, single_match
, 0)
164 # Same data as Entry 1
171 yield from set_cam(dut
, enable
, write_enable
, address
, data
)
173 yield from check_single_match(dut
, single_match
, 0)
182 yield from set_cam(dut
, enable
, write_enable
, address
, data
)
184 yield from check_all(dut
, multiple_match
, single_match
, address
, 0, 0, 0)
186 # Verify read_warning is not caused
194 yield from set_cam(dut
, enable
, write_enable
, address
, data
)
195 # Note there is no yield we immediately attempt to read in the next cycle
204 yield from set_cam(dut
, enable
, write_enable
, address
, data
)
206 yield from check_single_match(dut
, single_match
, 0)
213 run_simulation(dut
, tbench(dut
), vcd_name
="Waveforms/test_cam.vcd")
214 print("Cam Unit Test Success")
217 if __name__
== "__main__":