1 from nmigen
.compat
.sim
import run_simulation
3 from soc
.TestUtil
.test_helper
import assert_eq
, assert_ne
, assert_op
4 from soc
.TLB
.CamEntry
import CamEntry
6 # This function allows for the easy setting of values to the Cam Entry
8 # dut: The CamEntry being tested
9 # c (command): NA (0), Read (1), Write (2), Reserve (3)
10 # d (data): The data to be set
13 def set_cam_entry(dut
, c
, d
):
14 # Write desired values
15 yield dut
.command
.eq(c
)
16 yield dut
.data_in
.eq(d
)
19 yield dut
.command
.eq(0)
20 yield dut
.data_in
.eq(0)
23 # Checks the data state of the CAM entry
25 # dut: The CamEntry being tested
26 # d (Data): The expected data
27 # op (Operation): (0 => ==), (1 => !=)
30 def check_data(dut
, d
, op
):
31 out_d
= yield dut
.data
32 assert_op("Data", out_d
, d
, op
)
34 # Checks the match state of the CAM entry
36 # dut: The CamEntry being tested
37 # m (Match): The expected match
38 # op (Operation): (0 => ==), (1 => !=)
41 def check_match(dut
, m
, op
):
42 out_m
= yield dut
.match
43 assert_op("Match", out_m
, m
, op
)
45 # Checks the state of the CAM entry
47 # dut: The CamEntry being tested
48 # d (data): The expected data
49 # m (match): The expected match
50 # d_op (Operation): Operation for the data assertion (0 => ==), (1 => !=)
51 # m_op (Operation): Operation for the match assertion (0 => ==), (1 => !=)
54 def check_all(dut
, d
, m
, d_op
, m_op
):
55 yield from check_data(dut
, d
, d_op
)
56 yield from check_match(dut
, m
, m_op
)
58 # This tbench goes through the paces of testing the CamEntry module
59 # It is done by writing and then reading various combinations of key/data pairs
60 # and reading the results with varying keys to verify the resulting stored
69 yield from set_cam_entry(dut
, command
, data
)
70 yield from check_all(dut
, data
, match
, 0, 0)
76 yield from set_cam_entry(dut
, command
, data
)
77 yield from check_all(dut
, data
, match
, 1, 0)
83 yield from set_cam_entry(dut
, command
, data
)
84 yield from check_all(dut
, data
, match
, 0, 0)
90 yield from set_cam_entry(dut
, command
, data
)
92 yield from check_all(dut
, data
, match
, 0, 0)
98 yield from set_cam_entry(dut
, command
, data
)
99 yield from check_all(dut
, data
, match
, 0, 0)
105 yield from set_cam_entry(dut
, command
, data
)
106 yield from check_all(dut
, data
, match
, 0, 0)
108 # Extra clock cycle for waveform
114 run_simulation(dut
, tbench(dut
), vcd_name
="Waveforms/test_cam_entry.vcd")
115 print("CamEntry Unit Test Success")
118 if __name__
== "__main__":