src/unused/TLB/test/test_pte_entry.py

   1 from nmigen.compat.sim import run_simulation
   2
   3 from soc.TLB.PteEntry import PteEntry
   4
   5 from soc.TestUtil.test_helper import assert_op
   6
   7
   8 def set_entry(dut, i):
   9     yield dut.i.eq(i)
  10     yield
  11
  12
  13 def check_dirty(dut, d, op):
  14     out_d = yield dut.d
  15     assert_op("Dirty", out_d, d, op)
  16
  17
  18 def check_accessed(dut, a, op):
  19     out_a = yield dut.a
  20     assert_op("Accessed", out_a, a, op)
  21
  22
  23 def check_global(dut, o, op):
  24     out = yield dut.g
  25     assert_op("Global", out, o, op)
  26
  27
  28 def check_user(dut, o, op):
  29     out = yield dut.u
  30     assert_op("User Mode", out, o, op)
  31
  32
  33 def check_xwr(dut, o, op):
  34     out = yield dut.xwr
  35     assert_op("XWR", out, o, op)
  36
  37
  38 def check_asid(dut, o, op):
  39     out = yield dut.asid
  40     assert_op("ASID", out, o, op)
  41
  42
  43 def check_pte(dut, o, op):
  44     out = yield dut.pte
  45     assert_op("ASID", out, o, op)
  46
  47
  48 def check_valid(dut, v, op):
  49     out_v = yield dut.v
  50     assert_op("Valid", out_v, v, op)
  51
  52
  53 def check_all(dut, d, a, g, u, xwr, v, asid, pte):
  54     yield from check_dirty(dut, d, 0)
  55     yield from check_accessed(dut, a, 0)
  56     yield from check_global(dut, g, 0)
  57     yield from check_user(dut, u, 0)
  58     yield from check_xwr(dut, xwr, 0)
  59     yield from check_asid(dut, asid, 0)
  60     yield from check_pte(dut, pte, 0)
  61     yield from check_valid(dut, v, 0)
  62
  63
  64 def tbench(dut):
  65     # 80 bits represented. Ignore the MSB as it will be truncated
  66     # ASID is bits first 4 hex values (bits 64 - 78)
  67
  68     i = 0x7FFF0000000000000031
  69     dirty = 0
  70     access = 0
  71     glob = 1
  72     user = 1
  73     xwr = 0
  74     valid = 1
  75     asid = 0x7FFF
  76     pte = 0x0000000000000031
  77     yield from set_entry(dut, i)
  78     yield from check_all(dut, dirty, access, glob, user, xwr, valid, asid, pte)
  79
  80     i = 0x0FFF00000000000000FF
  81     dirty = 1
  82     access = 1
  83     glob = 1
  84     user = 1
  85     xwr = 7
  86     valid = 1
  87     asid = 0x0FFF
  88     pte = 0x00000000000000FF
  89     yield from set_entry(dut, i)
  90     yield from check_all(dut, dirty, access, glob, user, xwr, valid, asid, pte)
  91
  92     i = 0x0721000000001100001F
  93     dirty = 0
  94     access = 0
  95     glob = 0
  96     user = 1
  97     xwr = 7
  98     valid = 1
  99     asid = 0x0721
 100     pte = 0x000000001100001F
 101     yield from set_entry(dut, i)
 102     yield from check_all(dut, dirty, access, glob, user, xwr, valid, asid, pte)
 103
 104     yield
 105
 106
 107 def test_pteentry():
 108     dut = PteEntry(15, 64)
 109     run_simulation(dut, tbench(dut), vcd_name="Waveforms/test_pte_entry.vcd")
 110     print("PteEntry Unit Test Success")
 111
 112
 113 if __name__ == "__main__":
 114     test_pteentry()