src/unused/iommu/axi_rab/axi4_ar_buffer.py

   1 # Copyright 2018 ETH Zurich and University of Bologna.
   2 # Copyright and related rights are licensed under the Solderpad Hardware
   3 # License, Version 0.51 (the "License"); you may not use this file except in
   4 # compliance with the License.  You may obtain a copy of the License at
   5 # http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
   6 # or agreed to in writing, software, hardware and materials distributed under
   7 # this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
   8 # CONDITIONS OF ANY KIND, either express or implied. See the License for the
   9 # specific language governing permissions and limitations under the License.
  10
  11 # this file has been generated by sv2nmigen
  12
  13 from nmigen import Signal, Module, Const, Cat, Elaboratable
  14
  15 # module axi4_ar_buffer
  16 #  #(
  17 #    parameter AXI_ID_WIDTH   = 4,
  18 #    parameter AXI_USER_WIDTH = 4
  19 #  )
  20 #  (
  21 #    input  logic                      axi4_aclk,
  22 #    input  logic                      axi4_arstn,
  23 #
  24 #    input  logic   [AXI_ID_WIDTH-1:0] s_axi4_arid,
  25 #    input  logic               [31:0] s_axi4_araddr,
  26 #    input  logic                      s_axi4_arvalid,
  27 #    output logic                      s_axi4_arready,
  28 #    input  logic                [7:0] s_axi4_arlen,
  29 #    input  logic                [2:0] s_axi4_arsize,
  30 #    input  logic                [1:0] s_axi4_arburst,
  31 #    input  logic                      s_axi4_arlock,
  32 #    input  logic                [2:0] s_axi4_arprot,
  33 #    input  logic                [3:0] s_axi4_arcache,
  34 #    input  logic [AXI_USER_WIDTH-1:0] s_axi4_aruser,
  35 #
  36 #    output logic   [AXI_ID_WIDTH-1:0] m_axi4_arid,
  37 #    output logic               [31:0] m_axi4_araddr,
  38 #    output logic                      m_axi4_arvalid,
  39 #    input  logic                      m_axi4_arready,
  40 #    output logic                [7:0] m_axi4_arlen,
  41 #    output logic                [2:0] m_axi4_arsize,
  42 #    output logic                [1:0] m_axi4_arburst,
  43 #    output logic                      m_axi4_arlock,
  44 #    output logic                [2:0] m_axi4_arprot,
  45 #    output logic                [3:0] m_axi4_arcache,
  46 #    output logic [AXI_USER_WIDTH-1:0] m_axi4_aruser
  47 #  );
  48
  49
  50 class axi4_ar_buffer(Elaboratable):
  51
  52     def __init__(self):
  53         # self.axi4_aclk = Signal() # input
  54         # self.axi4_arstn = Signal() # input
  55         self.s_axi4_arid = Signal(AXI_ID_WIDTH)  # input
  56         self.s_axi4_araddr = Signal(32)  # input
  57         self.s_axi4_arvalid = Signal()  # input
  58         self.s_axi4_arready = Signal()  # output
  59         self.s_axi4_arlen = Signal(8)  # input
  60         self.s_axi4_arsize = Signal(3)  # input
  61         self.s_axi4_arburst = Signal(2)  # input
  62         self.s_axi4_arlock = Signal()  # input
  63         self.s_axi4_arprot = Signal(3)  # input
  64         self.s_axi4_arcache = Signal(4)  # input
  65         self.s_axi4_aruser = Signal(AXI_USER_WIDTH)  # input
  66         self.m_axi4_arid = Signal(AXI_ID_WIDTH)  # output
  67         self.m_axi4_araddr = Signal(32)  # output
  68         self.m_axi4_arvalid = Signal()  # output
  69         self.m_axi4_arready = Signal()  # input
  70         self.m_axi4_arlen = Signal(8)  # output
  71         self.m_axi4_arsize = Signal(3)  # output
  72         self.m_axi4_arburst = Signal(2)  # output
  73         self.m_axi4_arlock = Signal()  # output
  74         self.m_axi4_arprot = Signal(3)  # output
  75         self.m_axi4_arcache = Signal(4)  # output
  76         self.m_axi4_aruser = Signal(AXI_USER_WIDTH)  # output
  77
  78     def elaborate(self, platform=None):
  79         m = Module()
  80         #  #TODO use record types here
  81         #  wire [AXI_ID_WIDTH+AXI_USER_WIDTH+52:0] data_in;
  82         #  wire [AXI_ID_WIDTH+AXI_USER_WIDTH+52:0] data_out;
  83
  84         # assign data_in                                           [3:0] = s_axi4_arcache;
  85         # assign data_in                                           [6:4] = s_axi4_arprot;
  86         # assign data_in                                             [7] = s_axi4_arlock;
  87         # assign data_in                                           [9:8] = s_axi4_arburst;
  88         # assign data_in                                         [12:10] = s_axi4_arsize;
  89         # assign data_in                                         [20:13] = s_axi4_arlen;
  90         # assign data_in                                         [52:21] = s_axi4_araddr;
  91         # assign data_in                            [52+AXI_ID_WIDTH:53] = s_axi4_arid;
  92         # assign data_in[52+AXI_ID_WIDTH+AXI_USER_WIDTH:53+AXI_ID_WIDTH] = s_axi4_aruser;
  93         #
  94         # assign m_axi4_arcache = data_out[3:0];
  95         # assign m_axi4_arprot  = data_out[6:4];
  96         # assign m_axi4_arlock  = data_out[7];
  97         # assign m_axi4_arburst = data_out[9:8];
  98         # assign m_axi4_arsize  = data_out[12:10];
  99         # assign m_axi4_arlen   = data_out[20:13];
 100         # assign m_axi4_araddr  = data_out[52:21];
 101         # assign m_axi4_arid    = data_out[52+AXI_ID_WIDTH:53];
 102         # assign m_axi4_aruser  = data_out[52+AXI_ID_WIDTH+AXI_USER_WIDTH:53+AXI_ID_WIDTH];
 103
 104         # m.d.comb += self.m_axi4_arcache.eq(..)
 105         # m.d.comb += self.m_axi4_arprot.eq(..)
 106         # m.d.comb += self.m_axi4_arlock.eq(..)
 107         # m.d.comb += self.m_axi4_arburst.eq(..)
 108         # m.d.comb += self.m_axi4_arsize.eq(..)
 109         # m.d.comb += self.m_axi4_arlen.eq(..)
 110         # m.d.comb += self.m_axi4_araddr.eq(..)
 111         # m.d.comb += self.m_axi4_arid.eq(..)
 112         # m.d.comb += self.m_axi4_aruser.eq(..)
 113         return m
 114
 115 # TODO convert axi_buffer_rab.sv
 116 #
 117 #  axi_buffer_rab
 118 #    #(
 119 #      .DATA_WIDTH   ( AXI_ID_WIDTH+AXI_USER_WIDTH+53  ),
 120 #      .BUFFER_DEPTH ( 4                               )
 121 #      )
 122 #    u_buffer
 123 #    (
 124 #      .clk       ( axi4_aclk      ),
 125 #      .rstn      ( axi4_arstn     ),
 126 #      .valid_out ( m_axi4_arvalid ),
 127 #      .data_out  ( data_out       ),
 128 #      .ready_in  ( m_axi4_arready ),
 129 #      .valid_in  ( s_axi4_arvalid ),
 130 #      .data_in   ( data_in        ),
 131 #      .ready_out ( s_axi4_arready )
 132 #    );
 133 #
 134
 135 # endmodule