src/unused/iommu/axi_rab/axi4_ar_sender.py

   1 # this file has been generated by sv2nmigen
   2
   3 from nmigen import Signal, Module, Const, Cat, Elaboratable
   4
   5
   6 class axi4_ar_sender(Elaboratable):
   7
   8     def __init__(self):
   9         self.axi4_aclk = Signal()  # input
  10         self.axi4_arstn = Signal()  # input
  11         self.l1_done_o = Signal()  # output
  12         self.l1_accept_i = Signal()  # input
  13         self.l1_drop_i = Signal()  # input
  14         self.l1_save_i = Signal()  # input
  15         self.l2_done_o = Signal()  # output
  16         self.l2_accept_i = Signal()  # input
  17         self.l2_drop_i = Signal()  # input
  18         self.l2_sending_o = Signal()  # output
  19         self.l1_araddr_i = Signal(AXI_ADDR_WIDTH)  # input
  20         self.l2_araddr_i = Signal(AXI_ADDR_WIDTH)  # input
  21         self.s_axi4_arid = Signal(AXI_ID_WIDTH)  # input
  22         self.s_axi4_arvalid = Signal()  # input
  23         self.s_axi4_arready = Signal()  # output
  24         self.s_axi4_arlen = Signal(8)  # input
  25         self.s_axi4_arsize = Signal(3)  # input
  26         self.s_axi4_arburst = Signal(2)  # input
  27         self.s_axi4_arlock = Signal()  # input
  28         self.s_axi4_arprot = Signal(3)  # input
  29         self.s_axi4_arcache = Signal(4)  # input
  30         self.s_axi4_aruser = Signal(AXI_USER_WIDTH)  # input
  31         self.m_axi4_arid = Signal(AXI_ID_WIDTH)  # output
  32         self.m_axi4_araddr = Signal(AXI_ADDR_WIDTH)  # output
  33         self.m_axi4_arvalid = Signal()  # output
  34         self.m_axi4_arready = Signal()  # input
  35         self.m_axi4_arlen = Signal(8)  # output
  36         self.m_axi4_arsize = Signal(3)  # output
  37         self.m_axi4_arburst = Signal(2)  # output
  38         self.m_axi4_arlock = Signal()  # output
  39         self.m_axi4_arprot = Signal(3)  # output
  40         self.m_axi4_arcache = Signal(4)  # output
  41         self.m_axi4_aruser = Signal(AXI_USER_WIDTH)  # output
  42
  43     def elaborate(self, platform=None):
  44         m = Module()
  45         m.d.comb += self.l1_save.eq(self.None)
  46         m.d.comb += self.l1_done_o.eq(self.None)
  47         m.d.comb += self.m_axi4_arvalid.eq(self.None)
  48         m.d.comb += self.s_axi4_arready.eq(self.None)
  49         m.d.comb += self.m_axi4_aruser.eq(self.None)
  50         m.d.comb += self.m_axi4_arcache.eq(self.None)
  51         m.d.comb += self.m_axi4_arprot.eq(self.None)
  52         m.d.comb += self.m_axi4_arlock.eq(self.None)
  53         m.d.comb += self.m_axi4_arburst.eq(self.None)
  54         m.d.comb += self.m_axi4_arsize.eq(self.None)
  55         m.d.comb += self.m_axi4_arlen.eq(self.None)
  56         m.d.comb += self.m_axi4_araddr.eq(self.None)
  57         m.d.comb += self.m_axi4_arid.eq(self.None)
  58         m.d.comb += self.l2_sending_o.eq(self.None)
  59         m.d.comb += self.l2_sent.eq(self.None)
  60         m.d.comb += self.l2_done_o.eq(self.None)
  61         m.d.comb += self.m_axi4_aruser.eq(self.s_axi4_aruser)
  62         m.d.comb += self.m_axi4_arcache.eq(self.s_axi4_arcache)
  63         m.d.comb += self.m_axi4_arprot.eq(self.s_axi4_arprot)
  64         m.d.comb += self.m_axi4_arlock.eq(self.s_axi4_arlock)
  65         m.d.comb += self.m_axi4_arburst.eq(self.s_axi4_arburst)
  66         m.d.comb += self.m_axi4_arsize.eq(self.s_axi4_arsize)
  67         m.d.comb += self.m_axi4_arlen.eq(self.s_axi4_arlen)
  68         m.d.comb += self.m_axi4_araddr.eq(self.l1_araddr_i)
  69         m.d.comb += self.m_axi4_arid.eq(self.s_axi4_arid)
  70         m.d.comb += self.l2_sending_o.eq(self.1: 'b0)
  71         m.d.comb += self.l2_available_q.eq(self.1: 'b0)
  72         m.d.comb += self.l2_done_o.eq(self.1: 'b0)
  73         return m
  74
  75 # // Copyright 2018 ETH Zurich and University of Bologna.
  76 # // Copyright and related rights are licensed under the Solderpad Hardware
  77 # // License, Version 0.51 (the "License"); you may not use this file except in
  78 # // compliance with the License.  You may obtain a copy of the License at
  79 # // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
  80 # // or agreed to in writing, software, hardware and materials distributed under
  81 # // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
  82 # // CONDITIONS OF ANY KIND, either express or implied. See the License for the
  83 # // specific language governing permissions and limitations under the License.
  84 #
  85 # module axi4_ar_sender
  86 #  #(
  87 #    parameter AXI_ADDR_WIDTH = 40,
  88 #    parameter AXI_ID_WIDTH   = 4,
  89 #    parameter AXI_USER_WIDTH = 4,
  90 #    parameter ENABLE_L2TLB   = 0
  91 #  )
  92 #  (
  93 #    input  logic                      axi4_aclk,
  94 #    input  logic                      axi4_arstn,
  95 #
  96 #    output logic                      l1_done_o,
  97 #    input  logic                      l1_accept_i,
  98 #    input  logic                      l1_drop_i,
  99 #    input  logic                      l1_save_i,
 100 #
 101 #    output logic                      l2_done_o,
 102 #    input  logic                      l2_accept_i,
 103 #    input  logic                      l2_drop_i,
 104 #    output logic                      l2_sending_o,
 105 #
 106 #    input  logic [AXI_ADDR_WIDTH-1:0] l1_araddr_i,
 107 #    input  logic [AXI_ADDR_WIDTH-1:0] l2_araddr_i,
 108 #
 109 #    input  logic   [AXI_ID_WIDTH-1:0] s_axi4_arid,
 110 #    input  logic                      s_axi4_arvalid,
 111 #    output logic                      s_axi4_arready,
 112 #    input  logic                [7:0] s_axi4_arlen,
 113 #    input  logic                [2:0] s_axi4_arsize,
 114 #    input  logic                [1:0] s_axi4_arburst,
 115 #    input  logic                      s_axi4_arlock,
 116 #    input  logic                [2:0] s_axi4_arprot,
 117 #    input  logic                [3:0] s_axi4_arcache,
 118 #    input  logic [AXI_USER_WIDTH-1:0] s_axi4_aruser,
 119 #
 120 #    output logic   [AXI_ID_WIDTH-1:0] m_axi4_arid,
 121 #    output logic [AXI_ADDR_WIDTH-1:0] m_axi4_araddr,
 122 #    output logic                      m_axi4_arvalid,
 123 #    input  logic                      m_axi4_arready,
 124 #    output logic                [7:0] m_axi4_arlen,
 125 #    output logic                [2:0] m_axi4_arsize,
 126 #    output logic                [1:0] m_axi4_arburst,
 127 #    output logic                      m_axi4_arlock,
 128 #    output logic                [2:0] m_axi4_arprot,
 129 #    output logic                [3:0] m_axi4_arcache,
 130 #    output logic [AXI_USER_WIDTH-1:0] m_axi4_aruser
 131 #  );
 132 #
 133 #  logic l1_save;
 134 #
 135 #  logic l2_sent;
 136 #  logic l2_available_q;
 137 #
 138 #  assign l1_save      = l1_save_i & l2_available_q;
 139 #
 140 #  assign l1_done_o    = s_axi4_arvalid & s_axi4_arready ;
 141 #
 142 #  // if 1: accept and forward a transaction translated by L1
 143 #  //    2: drop or save request (if L2 slot not occupied already)
 144 #  assign m_axi4_arvalid = (s_axi4_arvalid & l1_accept_i) |
 145 #                          l2_sending_o;
 146 #  assign s_axi4_arready = (m_axi4_arvalid & m_axi4_arready & ~l2_sending_o) |
 147 #                          (s_axi4_arvalid & (l1_drop_i | l1_save));
 148 #
 149 # generate
 150 #  if (ENABLE_L2TLB == 1) begin
 151 #    logic [AXI_USER_WIDTH-1:0] l2_axi4_aruser  ;
 152 #    logic                [3:0] l2_axi4_arcache ;
 153 #    logic                [3:0] l2_axi4_arregion;
 154 #    logic                [3:0] l2_axi4_arqos   ;
 155 #    logic                [2:0] l2_axi4_arprot  ;
 156 #    logic                      l2_axi4_arlock  ;
 157 #    logic                [1:0] l2_axi4_arburst ;
 158 #    logic                [2:0] l2_axi4_arsize  ;
 159 #    logic                [7:0] l2_axi4_arlen   ;
 160 #    logic   [AXI_ID_WIDTH-1:0] l2_axi4_arid    ;
 161 #
 162 #    assign m_axi4_aruser  = l2_sending_o ? l2_axi4_aruser   : s_axi4_aruser;
 163 #    assign m_axi4_arcache = l2_sending_o ? l2_axi4_arcache  : s_axi4_arcache;
 164 #    assign m_axi4_arprot  = l2_sending_o ? l2_axi4_arprot   : s_axi4_arprot;
 165 #    assign m_axi4_arlock  = l2_sending_o ? l2_axi4_arlock   : s_axi4_arlock;
 166 #    assign m_axi4_arburst = l2_sending_o ? l2_axi4_arburst  : s_axi4_arburst;
 167 #    assign m_axi4_arsize  = l2_sending_o ? l2_axi4_arsize   : s_axi4_arsize;
 168 #    assign m_axi4_arlen   = l2_sending_o ? l2_axi4_arlen    : s_axi4_arlen;
 169 #    assign m_axi4_araddr  = l2_sending_o ? l2_araddr_i      : l1_araddr_i;
 170 #    assign m_axi4_arid    = l2_sending_o ? l2_axi4_arid     : s_axi4_arid;
 171 #
 172 #    // Buffer AXI signals in case of L1 miss
 173 #    always @(posedge axi4_aclk or negedge axi4_arstn) begin
 174 #      if (axi4_arstn == 1'b0) begin
 175 #        l2_axi4_aruser  <=  'b0;
 176 #        l2_axi4_arcache <=  'b0;
 177 #        l2_axi4_arprot  <=  'b0;
 178 #        l2_axi4_arlock  <= 1'b0;
 179 #        l2_axi4_arburst <=  'b0;
 180 #        l2_axi4_arsize  <=  'b0;
 181 #        l2_axi4_arlen   <=  'b0;
 182 #        l2_axi4_arid    <=  'b0;
 183 #      end else if (l1_save) begin
 184 #        l2_axi4_aruser  <= s_axi4_aruser;
 185 #        l2_axi4_arcache <= s_axi4_arcache;
 186 #        l2_axi4_arprot  <= s_axi4_arprot;
 187 #        l2_axi4_arlock  <= s_axi4_arlock;
 188 #        l2_axi4_arburst <= s_axi4_arburst;
 189 #        l2_axi4_arsize  <= s_axi4_arsize;
 190 #        l2_axi4_arlen   <= s_axi4_arlen;
 191 #        l2_axi4_arid    <= s_axi4_arid;
 192 #      end
 193 #    end
 194 #
 195 #    // signal that an l1_save_i can be accepted
 196 #    always @(posedge axi4_aclk or negedge axi4_arstn) begin
 197 #      if (axi4_arstn == 1'b0) begin
 198 #        l2_available_q <= 1'b1;
 199 #      end else if (l2_sent | l2_drop_i) begin
 200 #        l2_available_q <= 1'b1;
 201 #      end else if (l1_save) begin
 202 #        l2_available_q <= 1'b0;
 203 #      end
 204 #    end
 205 #
 206 #    assign l2_sending_o = l2_accept_i & ~l2_available_q;
 207 #    assign l2_sent      = l2_sending_o & m_axi4_arvalid & m_axi4_arready;
 208 #
 209 #    // if 1: having sent out a transaction translated by L2
 210 #    //    2: drop request (L2 slot is available again)
 211 #    assign l2_done_o    = l2_sent | l2_drop_i;
 212 #
 213 #  end else begin // !`ifdef ENABLE_L2TLB
 214 #    assign m_axi4_aruser  =  s_axi4_aruser;
 215 #    assign m_axi4_arcache =  s_axi4_arcache;
 216 #    assign m_axi4_arprot  =  s_axi4_arprot;
 217 #    assign m_axi4_arlock  =  s_axi4_arlock;
 218 #    assign m_axi4_arburst =  s_axi4_arburst;
 219 #    assign m_axi4_arsize  =  s_axi4_arsize;
 220 #    assign m_axi4_arlen   =  s_axi4_arlen;
 221 #    assign m_axi4_araddr  =  l1_araddr_i;
 222 #    assign m_axi4_arid    =  s_axi4_arid;
 223 #
 224 #    assign l2_sending_o   = 1'b0;
 225 #    assign l2_available_q = 1'b0;
 226 #    assign l2_done_o      = 1'b0;
 227 #  end // else: !if(ENABLE_L2TLB == 1)
 228 # endgenerate
 229 #
 230 # endmodule
 231 #
 232 #