src/unused/iommu/axi_rab/axi4_aw_buffer.py

   1 # this file has been generated by sv2nmigen
   2
   3 from nmigen import Signal, Module, Const, Cat, Elaboratable
   4
   5
   6 class axi4_aw_buffer(Elaboratable):
   7
   8     def __init__(self):
   9         self.axi4_aclk = Signal()  # input
  10         self.axi4_arstn = Signal()  # input
  11         self.s_axi4_awid = Signal(AXI_ID_WIDTH)  # input
  12         self.s_axi4_awaddr = Signal(32)  # input
  13         self.s_axi4_awvalid = Signal()  # input
  14         self.s_axi4_awready = Signal()  # output
  15         self.s_axi4_awlen = Signal(8)  # input
  16         self.s_axi4_awsize = Signal(3)  # input
  17         self.s_axi4_awburst = Signal(2)  # input
  18         self.s_axi4_awlock = Signal()  # input
  19         self.s_axi4_awprot = Signal(3)  # input
  20         self.s_axi4_awcache = Signal(4)  # input
  21         self.s_axi4_awregion = Signal(4)  # input
  22         self.s_axi4_awqos = Signal(4)  # input
  23         self.s_axi4_awuser = Signal(AXI_USER_WIDTH)  # input
  24         self.m_axi4_awid = Signal(AXI_ID_WIDTH)  # output
  25         self.m_axi4_awaddr = Signal(32)  # output
  26         self.m_axi4_awvalid = Signal()  # output
  27         self.m_axi4_awready = Signal()  # input
  28         self.m_axi4_awlen = Signal(8)  # output
  29         self.m_axi4_awsize = Signal(3)  # output
  30         self.m_axi4_awburst = Signal(2)  # output
  31         self.m_axi4_awlock = Signal()  # output
  32         self.m_axi4_awprot = Signal(3)  # output
  33         self.m_axi4_awcache = Signal(4)  # output
  34         self.m_axi4_awregion = Signal(4)  # output
  35         self.m_axi4_awqos = Signal(4)  # output
  36         self.m_axi4_awuser = Signal(AXI_USER_WIDTH)  # output
  37
  38     def elaborate(self, platform=None):
  39         m = Module()
  40         m.d.comb += self.None.eq(self.s_axi4_awcache)
  41         m.d.comb += self.None.eq(self.s_axi4_awprot)
  42         m.d.comb += self.None.eq(self.s_axi4_awlock)
  43         m.d.comb += self.None.eq(self.s_axi4_awburst)
  44         m.d.comb += self.None.eq(self.s_axi4_awsize)
  45         m.d.comb += self.None.eq(self.s_axi4_awlen)
  46         m.d.comb += self.None.eq(self.s_axi4_awaddr)
  47         m.d.comb += self.None.eq(self.s_axi4_awregion)
  48         m.d.comb += self.None.eq(self.s_axi4_awqos)
  49         m.d.comb += self.None.eq(self.s_axi4_awid)
  50         m.d.comb += self.None.eq(self.s_axi4_awuser)
  51         m.d.comb += self.m_axi4_awcache.eq(self.None)
  52         m.d.comb += self.m_axi4_awprot.eq(self.None)
  53         m.d.comb += self.m_axi4_awlock.eq(self.None)
  54         m.d.comb += self.m_axi4_awburst.eq(self.None)
  55         m.d.comb += self.m_axi4_awsize.eq(self.None)
  56         m.d.comb += self.m_axi4_awlen.eq(self.None)
  57         m.d.comb += self.m_axi4_awaddr.eq(self.None)
  58         m.d.comb += self.m_axi4_awregion.eq(self.None)
  59         m.d.comb += self.m_axi4_awqos.eq(self.None)
  60         m.d.comb += self.m_axi4_awid.eq(self.None)
  61         m.d.comb += self.m_axi4_awuser.eq(self.None)
  62         return m
  63
  64 # // Copyright 2018 ETH Zurich and University of Bologna.
  65 # // Copyright and related rights are licensed under the Solderpad Hardware
  66 # // License, Version 0.51 (the "License"); you may not use this file except in
  67 # // compliance with the License.  You may obtain a copy of the License at
  68 # // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
  69 # // or agreed to in writing, software, hardware and materials distributed under
  70 # // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
  71 # // CONDITIONS OF ANY KIND, either express or implied. See the License for the
  72 # // specific language governing permissions and limitations under the License.
  73 #
  74 # module axi4_aw_buffer
  75 #  #(
  76 #    parameter AXI_ID_WIDTH   = 4,
  77 #    parameter AXI_USER_WIDTH = 4
  78 #  )
  79 #  (
  80 #    input  logic                      axi4_aclk,
  81 #    input  logic                      axi4_arstn,
  82 #
  83 #    input  logic   [AXI_ID_WIDTH-1:0] s_axi4_awid,
  84 #    input  logic               [31:0] s_axi4_awaddr,
  85 #    input  logic                      s_axi4_awvalid,
  86 #    output logic                      s_axi4_awready,
  87 #    input  logic                [7:0] s_axi4_awlen,
  88 #    input  logic                [2:0] s_axi4_awsize,
  89 #    input  logic                [1:0] s_axi4_awburst,
  90 #    input  logic                      s_axi4_awlock,
  91 #    input  logic                [2:0] s_axi4_awprot,
  92 #    input  logic                [3:0] s_axi4_awcache,
  93 #    input  logic                [3:0] s_axi4_awregion,
  94 #    input  logic                [3:0] s_axi4_awqos,
  95 #    input  logic [AXI_USER_WIDTH-1:0] s_axi4_awuser,
  96 #
  97 #    output logic   [AXI_ID_WIDTH-1:0] m_axi4_awid,
  98 #    output logic               [31:0] m_axi4_awaddr,
  99 #    output logic                      m_axi4_awvalid,
 100 #    input  logic                      m_axi4_awready,
 101 #    output logic                [7:0] m_axi4_awlen,
 102 #    output logic                [2:0] m_axi4_awsize,
 103 #    output logic                [1:0] m_axi4_awburst,
 104 #    output logic                      m_axi4_awlock,
 105 #    output logic                [2:0] m_axi4_awprot,
 106 #    output logic                [3:0] m_axi4_awcache,
 107 #    output logic                [3:0] m_axi4_awregion,
 108 #    output logic                [3:0] m_axi4_awqos,
 109 #    output logic [AXI_USER_WIDTH-1:0] m_axi4_awuser
 110 #  );
 111 #
 112 #  wire [AXI_USER_WIDTH+AXI_ID_WIDTH+60:0] data_in;
 113 #  wire [AXI_USER_WIDTH+AXI_ID_WIDTH+60:0] data_out;
 114 #
 115 #  assign data_in                                            [3:0] = s_axi4_awcache;
 116 #  assign data_in                                            [6:4] = s_axi4_awprot;
 117 #  assign data_in                                              [7] = s_axi4_awlock;
 118 #  assign data_in                                            [9:8] = s_axi4_awburst;
 119 #  assign data_in                                          [12:10] = s_axi4_awsize;
 120 #  assign data_in                                          [20:13] = s_axi4_awlen;
 121 #  assign data_in                                          [52:21] = s_axi4_awaddr;
 122 #  assign data_in                                          [56:53] = s_axi4_awregion;
 123 #  assign data_in                                          [60:57] = s_axi4_awqos;
 124 #  assign data_in                             [60+AXI_ID_WIDTH:61] = s_axi4_awid;
 125 #  assign data_in [60+AXI_ID_WIDTH+AXI_USER_WIDTH:61+AXI_ID_WIDTH] = s_axi4_awuser;
 126 #
 127 #  assign m_axi4_awcache  = data_out[3:0];
 128 #  assign m_axi4_awprot   = data_out[6:4];
 129 #  assign m_axi4_awlock   = data_out[7];
 130 #  assign m_axi4_awburst  = data_out[9:8];
 131 #  assign m_axi4_awsize   = data_out[12:10];
 132 #  assign m_axi4_awlen    = data_out[20:13];
 133 #  assign m_axi4_awaddr   = data_out[52:21];
 134 #  assign m_axi4_awregion = data_out[56:53];
 135 #  assign m_axi4_awqos    = data_out[60:57];
 136 #  assign m_axi4_awid     = data_out[60+AXI_ID_WIDTH:61];
 137 #  assign m_axi4_awuser   = data_out[60+AXI_ID_WIDTH+AXI_USER_WIDTH:61+AXI_ID_WIDTH];
 138 #
 139 #  axi_buffer_rab
 140 #    #(
 141 #      .DATA_WIDTH   ( AXI_ID_WIDTH+AXI_USER_WIDTH+61  ),
 142 #      .BUFFER_DEPTH ( 4                               )
 143 #    )
 144 #    u_buffer
 145 #    (
 146 #      .clk       ( axi4_aclk      ),
 147 #      .rstn      ( axi4_arstn     ),
 148 #      .valid_out ( m_axi4_awvalid ),
 149 #      .data_out  ( data_out       ),
 150 #      .ready_in  ( m_axi4_awready ),
 151 #      .valid_in  ( s_axi4_awvalid ),
 152 #      .data_in   ( data_in        ),
 153 #      .ready_out ( s_axi4_awready )
 154 #    );
 155 # endmodule
 156 #
 157 #