1 # this file has been generated by sv2nmigen
3 from nmigen
import Signal
, Module
, Const
, Cat
, Elaboratable
6 class axi4_aw_sender(Elaboratable
):
9 self
.axi4_aclk
= Signal() # input
10 self
.axi4_arstn
= Signal() # input
11 self
.l1_done_o
= Signal() # output
12 self
.l1_accept_i
= Signal() # input
13 self
.l1_drop_i
= Signal() # input
14 self
.l1_save_i
= Signal() # input
15 self
.l2_done_o
= Signal() # output
16 self
.l2_accept_i
= Signal() # input
17 self
.l2_drop_i
= Signal() # input
18 self
.l2_sending_o
= Signal() # output
19 self
.l1_awaddr_i
= Signal(AXI_ADDR_WIDTH
) # input
20 self
.l2_awaddr_i
= Signal(AXI_ADDR_WIDTH
) # input
21 self
.s_axi4_awid
= Signal(AXI_ID_WIDTH
) # input
22 self
.s_axi4_awvalid
= Signal() # input
23 self
.s_axi4_awready
= Signal() # output
24 self
.s_axi4_awlen
= Signal(8) # input
25 self
.s_axi4_awsize
= Signal(3) # input
26 self
.s_axi4_awburst
= Signal(2) # input
27 self
.s_axi4_awlock
= Signal() # input
28 self
.s_axi4_awprot
= Signal(3) # input
29 self
.s_axi4_awcache
= Signal(4) # input
30 self
.s_axi4_awregion
= Signal(4) # input
31 self
.s_axi4_awqos
= Signal(4) # input
32 self
.s_axi4_awuser
= Signal(AXI_USER_WIDTH
) # input
33 self
.m_axi4_awid
= Signal(AXI_ID_WIDTH
) # output
34 self
.m_axi4_awaddr
= Signal(AXI_ADDR_WIDTH
) # output
35 self
.m_axi4_awvalid
= Signal() # output
36 self
.m_axi4_awready
= Signal() # input
37 self
.m_axi4_awlen
= Signal(8) # output
38 self
.m_axi4_awsize
= Signal(3) # output
39 self
.m_axi4_awburst
= Signal(2) # output
40 self
.m_axi4_awlock
= Signal() # output
41 self
.m_axi4_awprot
= Signal(3) # output
42 self
.m_axi4_awcache
= Signal(4) # output
43 self
.m_axi4_awregion
= Signal(4) # output
44 self
.m_axi4_awqos
= Signal(4) # output
45 self
.m_axi4_awuser
= Signal(AXI_USER_WIDTH
) # output
47 def elaborate(self
, platform
=None):
49 m
.d
.comb
+= self
.l1_save
.eq(self
.None)
50 m
.d
.comb
+= self
.l1_done_o
.eq(self
.None)
51 m
.d
.comb
+= self
.m_axi4_awvalid
.eq(self
.None)
52 m
.d
.comb
+= self
.s_axi4_awready
.eq(self
.None)
53 m
.d
.comb
+= self
.m_axi4_awuser
.eq(self
.None)
54 m
.d
.comb
+= self
.m_axi4_awcache
.eq(self
.None)
55 m
.d
.comb
+= self
.m_axi4_awregion
.eq(self
.None)
56 m
.d
.comb
+= self
.m_axi4_awqos
.eq(self
.None)
57 m
.d
.comb
+= self
.m_axi4_awprot
.eq(self
.None)
58 m
.d
.comb
+= self
.m_axi4_awlock
.eq(self
.None)
59 m
.d
.comb
+= self
.m_axi4_awburst
.eq(self
.None)
60 m
.d
.comb
+= self
.m_axi4_awsize
.eq(self
.None)
61 m
.d
.comb
+= self
.m_axi4_awlen
.eq(self
.None)
62 m
.d
.comb
+= self
.m_axi4_awaddr
.eq(self
.None)
63 m
.d
.comb
+= self
.m_axi4_awid
.eq(self
.None)
64 m
.d
.comb
+= self
.l2_sending_o
.eq(self
.None)
65 m
.d
.comb
+= self
.l2_sent
.eq(self
.None)
66 m
.d
.comb
+= self
.l2_done_o
.eq(self
.None)
67 m
.d
.comb
+= self
.m_axi4_awuser
.eq(self
.s_axi4_awuser
)
68 m
.d
.comb
+= self
.m_axi4_awcache
.eq(self
.s_axi4_awcache
)
69 m
.d
.comb
+= self
.m_axi4_awregion
.eq(self
.s_axi4_awregion
)
70 m
.d
.comb
+= self
.m_axi4_awqos
.eq(self
.s_axi4_awqos
)
71 m
.d
.comb
+= self
.m_axi4_awprot
.eq(self
.s_axi4_awprot
)
72 m
.d
.comb
+= self
.m_axi4_awlock
.eq(self
.s_axi4_awlock
)
73 m
.d
.comb
+= self
.m_axi4_awburst
.eq(self
.s_axi4_awburst
)
74 m
.d
.comb
+= self
.m_axi4_awsize
.eq(self
.s_axi4_awsize
)
75 m
.d
.comb
+= self
.m_axi4_awlen
.eq(self
.s_axi4_awlen
)
76 m
.d
.comb
+= self
.m_axi4_awaddr
.eq(self
.l1_awaddr_i
)
77 m
.d
.comb
+= self
.m_axi4_awid
.eq(self
.s_axi4_awid
)
78 m
.d
.comb
+= self
.l2_sending_o
.eq(self
.1: 'b0)
79 m.d.comb += self.l2_available_q.eq(self.1: 'b0
)
80 m
.d
.comb
+= self
.l2_done_o
.eq(self
.1: 'b0)
83 # // Copyright 2018 ETH Zurich and University of Bologna.
84 # // Copyright and related rights are licensed under the Solderpad Hardware
85 # // License, Version 0.51 (the "License"); you may not use this file except in
86 # // compliance with the License. You may obtain a copy of the License at
87 # // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
88 # // or agreed to in writing, software, hardware and materials distributed under
89 # // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
90 # // CONDITIONS OF ANY KIND, either express or implied. See the License for the
91 # // specific language governing permissions and limitations under the License.
93 # module axi4_aw_sender
95 # parameter AXI_ADDR_WIDTH = 40,
96 # parameter AXI_ID_WIDTH = 4,
97 # parameter AXI_USER_WIDTH = 4,
98 # parameter ENABLE_L2TLB = 0
101 # input logic axi4_aclk,
102 # input logic axi4_arstn,
104 # output logic l1_done_o,
105 # input logic l1_accept_i,
106 # input logic l1_drop_i,
107 # input logic l1_save_i,
109 # output logic l2_done_o,
110 # input logic l2_accept_i,
111 # input logic l2_drop_i,
112 # output logic l2_sending_o,
114 # input logic [AXI_ADDR_WIDTH-1:0] l1_awaddr_i,
115 # input logic [AXI_ADDR_WIDTH-1:0] l2_awaddr_i,
117 # input logic [AXI_ID_WIDTH-1:0] s_axi4_awid,
118 # input logic s_axi4_awvalid,
119 # output logic s_axi4_awready,
120 # input logic [7:0] s_axi4_awlen,
121 # input logic [2:0] s_axi4_awsize,
122 # input logic [1:0] s_axi4_awburst,
123 # input logic s_axi4_awlock,
124 # input logic [2:0] s_axi4_awprot,
125 # input logic [3:0] s_axi4_awcache,
126 # input logic [3:0] s_axi4_awregion,
127 # input logic [3:0] s_axi4_awqos,
128 # input logic [AXI_USER_WIDTH-1:0] s_axi4_awuser,
130 # output logic [AXI_ID_WIDTH-1:0] m_axi4_awid,
131 # output logic [AXI_ADDR_WIDTH-1:0] m_axi4_awaddr,
132 # output logic m_axi4_awvalid,
133 # input logic m_axi4_awready,
134 # output logic [7:0] m_axi4_awlen,
135 # output logic [2:0] m_axi4_awsize,
136 # output logic [1:0] m_axi4_awburst,
137 # output logic m_axi4_awlock,
138 # output logic [2:0] m_axi4_awprot,
139 # output logic [3:0] m_axi4_awcache,
140 # output logic [3:0] m_axi4_awregion,
141 # output logic [3:0] m_axi4_awqos,
142 # output logic [AXI_USER_WIDTH-1:0] m_axi4_awuser
148 # logic l2_available_q;
150 # assign l1_save = l1_save_i & l2_available_q;
152 # assign l1_done_o = s_axi4_awvalid & s_axi4_awready ;
154 # // if 1: accept and forward a transaction translated by L1
155 # // 2: drop or save request (if L2 slot not occupied already)
156 # assign m_axi4_awvalid = (s_axi4_awvalid & l1_accept_i) |
158 # assign s_axi4_awready = (m_axi4_awvalid & m_axi4_awready & ~l2_sending_o) |
159 # (s_axi4_awvalid & (l1_drop_i | l1_save));
162 # if (ENABLE_L2TLB == 1) begin
163 # logic [AXI_USER_WIDTH-1:0] l2_axi4_awuser ;
164 # logic [3:0] l2_axi4_awcache ;
165 # logic [3:0] l2_axi4_awregion;
166 # logic [3:0] l2_axi4_awqos ;
167 # logic [2:0] l2_axi4_awprot ;
168 # logic l2_axi4_awlock ;
169 # logic [1:0] l2_axi4_awburst ;
170 # logic [2:0] l2_axi4_awsize ;
171 # logic [7:0] l2_axi4_awlen ;
172 # logic [AXI_ID_WIDTH-1:0] l2_axi4_awid ;
174 # assign m_axi4_awuser = l2_sending_o ? l2_axi4_awuser : s_axi4_awuser;
175 # assign m_axi4_awcache = l2_sending_o ? l2_axi4_awcache : s_axi4_awcache;
176 # assign m_axi4_awregion = l2_sending_o ? l2_axi4_awregion : s_axi4_awregion;
177 # assign m_axi4_awqos = l2_sending_o ? l2_axi4_awqos : s_axi4_awqos;
178 # assign m_axi4_awprot = l2_sending_o ? l2_axi4_awprot : s_axi4_awprot;
179 # assign m_axi4_awlock = l2_sending_o ? l2_axi4_awlock : s_axi4_awlock;
180 # assign m_axi4_awburst = l2_sending_o ? l2_axi4_awburst : s_axi4_awburst;
181 # assign m_axi4_awsize = l2_sending_o ? l2_axi4_awsize : s_axi4_awsize;
182 # assign m_axi4_awlen = l2_sending_o ? l2_axi4_awlen : s_axi4_awlen;
183 # assign m_axi4_awaddr = l2_sending_o ? l2_awaddr_i : l1_awaddr_i;
184 # assign m_axi4_awid = l2_sending_o ? l2_axi4_awid : s_axi4_awid;
186 # // buffer AXI signals in case of L1 miss
187 # always @(posedge axi4_aclk or negedge axi4_arstn) begin
188 # if (axi4_arstn == 1'b0
) begin
189 # l2_axi4_awuser <= 'b0;
190 # l2_axi4_awcache <= 'b0;
191 # l2_axi4_awregion <= 'b0;
192 # l2_axi4_awqos <= 'b0;
193 # l2_axi4_awprot <= 'b0;
194 # l2_axi4_awlock <= 1'b0;
195 # l2_axi4_awburst <= 'b0;
196 # l2_axi4_awsize <= 'b0;
197 # l2_axi4_awlen <= 'b0;
198 # l2_axi4_awid <= 'b0;
199 # end else if (l1_save) begin
200 # l2_axi4_awuser <= s_axi4_awuser;
201 # l2_axi4_awcache <= s_axi4_awcache;
202 # l2_axi4_awregion <= s_axi4_awregion;
203 # l2_axi4_awqos <= s_axi4_awqos;
204 # l2_axi4_awprot <= s_axi4_awprot;
205 # l2_axi4_awlock <= s_axi4_awlock;
206 # l2_axi4_awburst <= s_axi4_awburst;
207 # l2_axi4_awsize <= s_axi4_awsize;
208 # l2_axi4_awlen <= s_axi4_awlen;
209 # l2_axi4_awid <= s_axi4_awid;
213 # // signal that an l1_save_i can be accepted
214 # always @(posedge axi4_aclk or negedge axi4_arstn) begin
215 # if (axi4_arstn == 1'b0) begin
216 # l2_available_q <= 1'b1;
217 # end else if (l2_sent | l2_drop_i) begin
218 # l2_available_q <= 1'b1;
219 # end else if (l1_save) begin
220 # l2_available_q <= 1'b0;
224 # assign l2_sending_o = l2_accept_i & ~l2_available_q;
225 # assign l2_sent = l2_sending_o & m_axi4_awvalid & m_axi4_awready;
227 # // if 1: having sent out a transaction translated by L2
228 # // 2: drop request (L2 slot is available again)
229 # assign l2_done_o = l2_sent | l2_drop_i;
231 # end else begin // !`ifdef ENABLE_L2TLB
232 # assign m_axi4_awuser = s_axi4_awuser;
233 # assign m_axi4_awcache = s_axi4_awcache;
234 # assign m_axi4_awregion = s_axi4_awregion;
235 # assign m_axi4_awqos = s_axi4_awqos;
236 # assign m_axi4_awprot = s_axi4_awprot;
237 # assign m_axi4_awlock = s_axi4_awlock;
238 # assign m_axi4_awburst = s_axi4_awburst;
239 # assign m_axi4_awsize = s_axi4_awsize;
240 # assign m_axi4_awlen = s_axi4_awlen;
241 # assign m_axi4_awaddr = l1_awaddr_i;
242 # assign m_axi4_awid = s_axi4_awid;
244 # assign l2_sending_o = 1'b0;
245 # assign l2_available_q = 1'b0;
246 # assign l2_done_o = 1'b0;
247 # end // !`ifdef ENABLE_L2TLB