src/unused/iommu/axi_rab/axi4_b_sender.py

   1 # this file has been generated by sv2nmigen
   2
   3 from nmigen import Signal, Module, Const, Cat, Elaboratable
   4
   5
   6 class axi4_b_sender(Elaboratable):
   7
   8     def __init__(self):
   9         self.axi4_aclk = Signal()  # input
  10         self.axi4_arstn = Signal()  # input
  11         self.drop_i = Signal()  # input
  12         self.done_o = Signal()  # output
  13         self.id_i = Signal(AXI_ID_WIDTH)  # input
  14         self.prefetch_i = Signal()  # input
  15         self.hit_i = Signal()  # input
  16         self.s_axi4_bid = Signal(AXI_ID_WIDTH)  # output
  17         self.s_axi4_bresp = Signal(2)  # output
  18         self.s_axi4_bvalid = Signal()  # output
  19         self.s_axi4_buser = Signal(AXI_USER_WIDTH)  # output
  20         self.s_axi4_bready = Signal()  # input
  21         self.m_axi4_bid = Signal(AXI_ID_WIDTH)  # input
  22         self.m_axi4_bresp = Signal(2)  # input
  23         self.m_axi4_bvalid = Signal()  # input
  24         self.m_axi4_buser = Signal(AXI_USER_WIDTH)  # input
  25         self.m_axi4_bready = Signal()  # output
  26
  27     def elaborate(self, platform=None):
  28         m = Module()
  29         m.d.comb += self.fifo_push.eq(self.None)
  30         m.d.comb += self.done_o.eq(self.fifo_push)
  31         m.d.comb += self.fifo_pop.eq(self.None)
  32         m.d.comb += self.s_axi4_buser.eq(self.None)
  33         m.d.comb += self.s_axi4_bid.eq(self.None)
  34         m.d.comb += self.s_axi4_bresp.eq(self.None)
  35         m.d.comb += self.s_axi4_bvalid.eq(self.None)
  36         m.d.comb += self.m_axi4_bready.eq(self.None)
  37         return m
  38
  39 # // Copyright 2018 ETH Zurich and University of Bologna.
  40 # // Copyright and related rights are licensed under the Solderpad Hardware
  41 # // License, Version 0.51 (the "License"); you may not use this file except in
  42 # // compliance with the License.  You may obtain a copy of the License at
  43 # // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
  44 # // or agreed to in writing, software, hardware and materials distributed under
  45 # // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
  46 # // CONDITIONS OF ANY KIND, either express or implied. See the License for the
  47 # // specific language governing permissions and limitations under the License.
  48 #
  49 # module axi4_b_sender
  50 #  #(
  51 #    parameter AXI_ID_WIDTH   = 10,
  52 #    parameter AXI_USER_WIDTH = 4
  53 #  )
  54 #  (
  55 #    input  logic                      axi4_aclk,
  56 #    input  logic                      axi4_arstn,
  57 #
  58 #    input  logic                      drop_i,
  59 #    output logic                      done_o,
  60 #    input  logic   [AXI_ID_WIDTH-1:0] id_i,
  61 #    input  logic                      prefetch_i,
  62 #    input  logic                      hit_i,
  63 #
  64 #    output logic   [AXI_ID_WIDTH-1:0] s_axi4_bid,
  65 #    output logic                [1:0] s_axi4_bresp,
  66 #    output logic                      s_axi4_bvalid,
  67 #    output logic [AXI_USER_WIDTH-1:0] s_axi4_buser,
  68 #    input  logic                      s_axi4_bready,
  69 #
  70 #    input  logic   [AXI_ID_WIDTH-1:0] m_axi4_bid,
  71 #    input  logic                [1:0] m_axi4_bresp,
  72 #    input  logic                      m_axi4_bvalid,
  73 #    input  logic [AXI_USER_WIDTH-1:0] m_axi4_buser,
  74 #    output logic                      m_axi4_bready
  75 #  );
  76 #
  77 #  logic                    fifo_valid;
  78 #  logic                    fifo_pop;
  79 #  logic                    fifo_push;
  80 #  logic                    fifo_ready;
  81 #  logic [AXI_ID_WIDTH-1:0] id;
  82 #  logic                    prefetch;
  83 #  logic                    hit;
  84 #
  85 #  logic                    dropping;
  86 #
  87 #  axi_buffer_rab
  88 #    #(
  89 #      .DATA_WIDTH   ( 2+AXI_ID_WIDTH  ),
  90 #      .BUFFER_DEPTH ( 4               )
  91 #      )
  92 #    u_fifo
  93 #      (
  94 #        .clk       ( axi4_aclk                 ),
  95 #        .rstn      ( axi4_arstn                ),
  96 #        // Pop
  97 #        .data_out  ( {prefetch,   hit,   id}   ),
  98 #        .valid_out ( fifo_valid                ),
  99 #        .ready_in  ( fifo_pop                  ),
 100 #        // Push
 101 #        .valid_in  ( fifo_push                 ),
 102 #        .data_in   ( {prefetch_i, hit_i, id_i} ),
 103 #        .ready_out ( fifo_ready                )
 104 #      );
 105 #
 106 #  assign fifo_push = drop_i & fifo_ready;
 107 #  assign done_o    = fifo_push;
 108 #
 109 #  assign fifo_pop  = dropping & s_axi4_bready;
 110 #
 111 #  always @ (posedge axi4_aclk or negedge axi4_arstn) begin
 112 #    if (axi4_arstn == 1'b0) begin
 113 #      dropping <= 1'b0;
 114 #    end else begin
 115 #      if (fifo_valid && ~dropping)
 116 #        dropping <= 1'b1;
 117 #      else if (fifo_pop)
 118 #        dropping <= 1'b0;
 119 #    end
 120 #  end
 121 #
 122 #  assign s_axi4_buser  = dropping ? {AXI_USER_WIDTH{1'b0}} : m_axi4_buser;
 123 #  assign s_axi4_bid    = dropping ? id : m_axi4_bid;
 124 #
 125 #  assign s_axi4_bresp  = (dropping & prefetch & hit) ? 2'b00 : // prefetch hit, mutli, prot
 126 #                         (dropping & prefetch      ) ? 2'b10 : // prefetch miss
 127 #                         (dropping            & hit) ? 2'b10 : // non-prefetch multi, prot
 128 #                         (dropping                 ) ? 2'b10 : // non-prefetch miss
 129 #                         m_axi4_bresp;
 130 #
 131 #  assign s_axi4_bvalid =  dropping | m_axi4_bvalid;
 132 #  assign m_axi4_bready = ~dropping & s_axi4_bready;
 133 #
 134 # endmodule
 135 #
 136 #