src/unused/iommu/axi_rab/fsm.py

   1 # this file has been generated by sv2nmigen
   2
   3 from nmigen import Signal, Module, Const, Cat, Elaboratable
   4
   5
   6 class fsm(Elaboratable):
   7
   8     def __init__(self):
   9         self.Clk_CI = Signal()  # input
  10         self.Rst_RBI = Signal()  # input
  11         self.port1_addr_valid_i = Signal()  # input
  12         self.port2_addr_valid_i = Signal()  # input
  13         self.port1_sent_i = Signal()  # input
  14         self.port2_sent_i = Signal()  # input
  15         self.select_i = Signal()  # input
  16         self.no_hit_i = Signal()  # input
  17         self.multi_hit_i = Signal()  # input
  18         self.no_prot_i = Signal()  # input
  19         self.prefetch_i = Signal()  # input
  20         self.out_addr_i = Signal(AXI_M_ADDR_WIDTH)  # input
  21         self.cache_coherent_i = Signal()  # input
  22         self.port1_accept_o = Signal()  # output
  23         self.port1_drop_o = Signal()  # output
  24         self.port1_miss_o = Signal()  # output
  25         self.port2_accept_o = Signal()  # output
  26         self.port2_drop_o = Signal()  # output
  27         self.port2_miss_o = Signal()  # output
  28         self.out_addr_o = Signal(AXI_M_ADDR_WIDTH)  # output
  29         self.cache_coherent_o = Signal()  # output
  30         self.miss_o = Signal()  # output
  31         self.multi_o = Signal()  # output
  32         self.prot_o = Signal()  # output
  33         self.prefetch_o = Signal()  # output
  34         self.in_addr_i = Signal(AXI_S_ADDR_WIDTH)  # input
  35         self.in_id_i = Signal(AXI_ID_WIDTH)  # input
  36         self.in_len_i = Signal(8)  # input
  37         self.in_user_i = Signal(AXI_USER_WIDTH)  # input
  38         self.in_addr_o = Signal(AXI_S_ADDR_WIDTH)  # output
  39         self.in_id_o = Signal(AXI_ID_WIDTH)  # output
  40         self.in_len_o = Signal(8)  # output
  41         self.in_user_o = Signal(AXI_USER_WIDTH)  # output
  42
  43     def elaborate(self, platform=None):
  44         m = Module()
  45         return m
  46
  47
  48 # // Copyright 2018 ETH Zurich and University of Bologna.
  49 # // Copyright and related rights are licensed under the Solderpad Hardware
  50 # // License, Version 0.51 (the "License"); you may not use this file except in
  51 # // compliance with the License.  You may obtain a copy of the License at
  52 # // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
  53 # // or agreed to in writing, software, hardware and materials distributed under
  54 # // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
  55 # // CONDITIONS OF ANY KIND, either express or implied. See the License for the
  56 # // specific language governing permissions and limitations under the License.
  57 #
  58 # //`timescale 1ns / 1ps
  59 #
  60 # module fsm
  61 #  #(
  62 #    parameter AXI_M_ADDR_WIDTH = 40,
  63 #    parameter AXI_S_ADDR_WIDTH = 32,
  64 #    parameter AXI_ID_WIDTH     = 8,
  65 #    parameter AXI_USER_WIDTH   = 6
  66 #  )
  67 #  (
  68 #    input  logic                        Clk_CI,
  69 #    input  logic                        Rst_RBI,
  70 #
  71 #    input  logic                        port1_addr_valid_i,
  72 #    input  logic                        port2_addr_valid_i,
  73 #    input  logic                        port1_sent_i,
  74 #    input  logic                        port2_sent_i,
  75 #    input  logic                        select_i,
  76 #    input  logic                        no_hit_i,
  77 #    input  logic                        multi_hit_i,
  78 #    input  logic                        no_prot_i,
  79 #    input  logic                        prefetch_i,
  80 #    input  logic [AXI_M_ADDR_WIDTH-1:0] out_addr_i,
  81 #    input  logic                        cache_coherent_i,
  82 #    output logic                        port1_accept_o,
  83 #    output logic                        port1_drop_o,
  84 #    output logic                        port1_miss_o,
  85 #    output logic                        port2_accept_o,
  86 #    output logic                        port2_drop_o,
  87 #    output logic                        port2_miss_o,
  88 #    output logic [AXI_M_ADDR_WIDTH-1:0] out_addr_o,
  89 #    output logic                        cache_coherent_o,
  90 #    output logic                        miss_o,
  91 #    output logic                        multi_o,
  92 #    output logic                        prot_o,
  93 #    output logic                        prefetch_o,
  94 #    input  logic [AXI_S_ADDR_WIDTH-1:0] in_addr_i,
  95 #    input  logic     [AXI_ID_WIDTH-1:0] in_id_i,
  96 #    input  logic                  [7:0] in_len_i,
  97 #    input  logic   [AXI_USER_WIDTH-1:0] in_user_i,
  98 #    output logic [AXI_S_ADDR_WIDTH-1:0] in_addr_o,
  99 #    output logic     [AXI_ID_WIDTH-1:0] in_id_o,
 100 #    output logic                  [7:0] in_len_o,
 101 #    output logic   [AXI_USER_WIDTH-1:0] in_user_o
 102 #  );
 103 #
 104 """  #docstring_begin
 105
 106   //-------------Internal Signals----------------------
 107
 108   typedef enum logic           {IDLE, WAIT} state_t;
 109   logic                        state_SP; // Present state
 110   logic                        state_SN; // Next State
 111
 112   logic                        port1_accept_SN;
 113   logic                        port1_drop_SN;
 114   logic                        port1_miss_SN;
 115   logic                        port2_accept_SN;
 116   logic                        port2_drop_SN;
 117   logic                        port2_miss_SN;
 118   logic                        miss_SN;
 119   logic                        multi_SN;
 120   logic                        prot_SN;
 121   logic                        prefetch_SN;
 122   logic                        cache_coherent_SN;
 123   logic [AXI_M_ADDR_WIDTH-1:0] out_addr_DN;
 124
 125   logic                        out_reg_en_S;
 126
 127   //----------FSM comb------------------------------
 128
 129   always_comb begin: FSM_COMBO
 130     state_SN          = state_SP;
 131
 132     port1_accept_SN   = 1'b0;
 133     port1_drop_SN     = 1'b0;
 134     port1_miss_SN     = 1'b0;
 135     port2_accept_SN   = 1'b0;
 136     port2_drop_SN     = 1'b0;
 137     port2_miss_SN     = 1'b0;
 138     miss_SN           = 1'b0;
 139     multi_SN          = 1'b0;
 140     prot_SN           = 1'b0;
 141     prefetch_SN       = 1'b0;
 142     cache_coherent_SN = 1'b0;
 143     out_addr_DN       =   '0;
 144
 145     out_reg_en_S      = 1'b0; // by default hold register output
 146
 147     unique case(state_SP)
 148         IDLE :
 149           if ( (port1_addr_valid_i & select_i) | (port2_addr_valid_i & ~select_i) ) begin
 150             out_reg_en_S = 1'b1;
 151             state_SN     = WAIT;
 152
 153             // Select inputs for output registers
 154             if          (port1_addr_valid_i & select_i) begin
 155               port1_accept_SN = ~(no_hit_i | multi_hit_i | ~no_prot_i | prefetch_i);
 156               port1_drop_SN   =  (no_hit_i | multi_hit_i | ~no_prot_i | prefetch_i);
 157               port1_miss_SN   =   no_hit_i;
 158               port2_accept_SN = 1'b0;
 159               port2_drop_SN   = 1'b0;
 160               port2_miss_SN   = 1'b0;
 161             end else if (port2_addr_valid_i & ~select_i) begin
 162               port1_accept_SN = 1'b0;
 163               port1_drop_SN   = 1'b0;
 164               port1_miss_SN   = 1'b0;
 165               port2_accept_SN = ~(no_hit_i | multi_hit_i | ~no_prot_i | prefetch_i);
 166               port2_drop_SN   =  (no_hit_i | multi_hit_i | ~no_prot_i | prefetch_i);
 167               port2_miss_SN   =   no_hit_i;
 168             end
 169
 170             miss_SN           = port1_miss_SN | port2_miss_SN;
 171             multi_SN          = multi_hit_i;
 172             prot_SN           = ~no_prot_i;
 173             prefetch_SN       = ~no_hit_i & prefetch_i;
 174
 175             cache_coherent_SN = cache_coherent_i;
 176             out_addr_DN       = out_addr_i;
 177           end
 178
 179         WAIT :
 180           if ( port1_sent_i | port2_sent_i ) begin
 181             out_reg_en_S = 1'b1; // "clear" the register
 182             state_SN     = IDLE;
 183           end
 184
 185         default : begin
 186            state_SN      = IDLE;
 187         end
 188       endcase
 189     end
 190
 191   //----------FSM seq-------------------------------
 192
 193   always_ff @(posedge Clk_CI, negedge Rst_RBI) begin: FSM_SEQ
 194     if (Rst_RBI == 1'b0)
 195       state_SP <= IDLE;
 196     else
 197       state_SP <= state_SN;
 198   end
 199
 200   //----------Output seq--------------------------
 201
 202   always_ff @(posedge Clk_CI, negedge Rst_RBI) begin: OUTPUT_SEQ
 203     if (Rst_RBI == 1'b0) begin
 204       port1_accept_o   = 1'b0;
 205       port1_drop_o     = 1'b0;
 206       port1_miss_o     = 1'b0;
 207       port2_accept_o   = 1'b0;
 208       port2_drop_o     = 1'b0;
 209       port2_miss_o     = 1'b0;
 210       miss_o           = 1'b0;
 211       multi_o          = 1'b0;
 212       prot_o           = 1'b0;
 213       prefetch_o       = 1'b0;
 214       cache_coherent_o = 1'b0;
 215       out_addr_o       =   '0;
 216       in_addr_o        =   '0;
 217       in_id_o          =   '0;
 218       in_len_o         =   '0;
 219       in_user_o        =   '0;
 220     end else if (out_reg_en_S == 1'b1) begin
 221       port1_accept_o   = port1_accept_SN;
 222       port1_drop_o     = port1_drop_SN;
 223       port1_miss_o     = port1_miss_SN;
 224       port2_accept_o   = port2_accept_SN;
 225       port2_drop_o     = port2_drop_SN;
 226       port2_miss_o     = port2_miss_SN;
 227       miss_o           = miss_SN;
 228       multi_o          = multi_SN;
 229       prot_o           = prot_SN;
 230       prefetch_o       = prefetch_SN;
 231       cache_coherent_o = cache_coherent_SN;
 232       out_addr_o       = out_addr_DN;
 233       in_addr_o        = in_addr_i;
 234       in_id_o          = in_id_i;
 235       in_len_o         = in_len_i;
 236       in_user_o        = in_user_i;
 237     end
 238   end // block: OUTPUT_SEQ
 239 """
 240 #
 241 # endmodule
 242 #
 243 #