src/unused/iommu/axi_rab/test/test_ram_tp_no_change.py

   1 from ram_tp_write_first import ram_tp_write_first
   2 from nmigen.compat.sim import run_simulation
   3 import sys
   4 sys.path.append("../")
   5
   6
   7 def tbench(dut):
   8     yield dut.we.eq(1)
   9     for i in range(0, 255):
  10         yield dut.addr0.eq(i)
  11         yield dut.d_i.eq(i)
  12         yield
  13
  14
  15 if __name__ == "__main__":
  16     dut = ram_tp_write_first()
  17     run_simulation(dut, tbench(dut), vcd_name="ram_tp_write_first.vcd")
  18     print("ram_tp_write_first Unit Test Success")