unused_please_ignore_completely/TLB/CamEntry.py

   1 from nmigen import Module, Signal, Elaboratable
   2
   3
   4 class CamEntry(Elaboratable):
   5     """ Content Addressable Memory (CAM) Entry
   6
   7         The purpose of this module is to represent an entry within a CAM.
   8         This module when given a read command will compare  the given data
   9         and output whether a match was found or not. When given a write
  10         command it will write the given data into internal registers.
  11     """
  12
  13     def __init__(self, data_size):
  14         """ Arguments:
  15             * data_size: (bit count) The size of the data
  16         """
  17         # Input
  18         self.command = Signal(2) # 00 => NA 01 => Read 10 => Write 11 => Reset
  19         self.data_in = Signal(data_size) # Data input when writing
  20
  21         # Output
  22         self.match = Signal(1) # Result of the internal/input key comparison
  23         self.data = Signal(data_size)
  24
  25     def elaborate(self, platform=None):
  26         m = Module()
  27         with m.Switch(self.command):
  28             with m.Case("00"):
  29                 m.d.sync += self.match.eq(0)
  30             with m.Case("01"):
  31                 with m.If(self.data == self.data_in):
  32                     m.d.sync += self.match.eq(1)
  33                 with m.Else():
  34                     m.d.sync += self.match.eq(0)
  35             with m.Case("10"):
  36                 m.d.sync += [
  37                     self.data.eq(self.data_in),
  38                     self.match.eq(0)
  39                 ]
  40             with m.Case():
  41                 m.d.sync += [
  42                     self.match.eq(0),
  43                     self.data.eq(0)
  44                 ]
  45
  46         return m