Allow the formal engine to perform a same-cycle result in the ALU
[soc.git] / unused_please_ignore_completely / TLB / ariane / test / test_tlb.py
1 from nmigen.compat.sim import run_simulation
2
3 from soc.TLB.ariane.tlb import TLB
4
5
6 def set_vaddr(addr):
7 yield dut.lu_vaddr_i.eq(addr)
8 yield dut.update_i.vpn.eq(addr >> 12)
9
10
11 def tbench(dut):
12 yield dut.lu_access_i.eq(1)
13 yield dut.lu_asid_i.eq(1)
14 yield dut.update_i.valid.eq(1)
15 yield dut.update_i.is_1G.eq(0)
16 yield dut.update_i.is_2M.eq(0)
17 yield dut.update_i.asid.eq(1)
18 yield dut.update_i.content.ppn.eq(0)
19 yield dut.update_i.content.rsw.eq(0)
20 yield dut.update_i.content.r.eq(1)
21
22 yield
23
24 addr = 0x80000
25 yield from set_vaddr(addr)
26 yield
27
28 addr = 0x90001
29 yield from set_vaddr(addr)
30 yield
31
32 addr = 0x28000000
33 yield from set_vaddr(addr)
34 yield
35
36 addr = 0x28000001
37 yield from set_vaddr(addr)
38
39 addr = 0x28000001
40 yield from set_vaddr(addr)
41 yield
42
43 addr = 0x1000040000
44 yield from set_vaddr(addr)
45 yield
46
47 addr = 0x1000040001
48 yield from set_vaddr(addr)
49 yield
50
51 yield dut.update_i.is_1G.eq(1)
52 addr = 0x2040000
53 yield from set_vaddr(addr)
54 yield
55
56 yield dut.update_i.is_1G.eq(1)
57 addr = 0x2040001
58 yield from set_vaddr(addr)
59 yield
60
61 yield
62
63
64 if __name__ == "__main__":
65 dut = TLB()
66 run_simulation(dut, tbench(dut), vcd_name="test_tlb.vcd")
67 print("TLB Unit Test Success")