unused_please_ignore_completely/TLB/test/test_cam_entry.py

   1 from nmigen.compat.sim import run_simulation
   2
   3 from soc.TestUtil.test_helper import assert_eq, assert_ne, assert_op
   4 from soc.TLB.CamEntry import CamEntry
   5
   6 # This function allows for the easy setting of values to the Cam Entry
   7 # Arguments:
   8 #   dut: The CamEntry being tested
   9 #   c (command): NA (0), Read (1), Write (2), Reserve (3)
  10 #   d (data): The data to be set
  11
  12
  13 def set_cam_entry(dut, c, d):
  14     # Write desired values
  15     yield dut.command.eq(c)
  16     yield dut.data_in.eq(d)
  17     yield
  18     # Reset all lines
  19     yield dut.command.eq(0)
  20     yield dut.data_in.eq(0)
  21     yield
  22
  23 # Checks the data state of the CAM entry
  24 # Arguments:
  25 #   dut: The CamEntry being tested
  26 #   d (Data): The expected data
  27 #   op (Operation): (0 => ==), (1 => !=)
  28
  29
  30 def check_data(dut, d, op):
  31     out_d = yield dut.data
  32     assert_op("Data", out_d, d, op)
  33
  34 # Checks the match state of the CAM entry
  35 # Arguments:
  36 #   dut: The CamEntry being tested
  37 #   m (Match): The expected match
  38 #   op (Operation): (0 => ==), (1 => !=)
  39
  40
  41 def check_match(dut, m, op):
  42     out_m = yield dut.match
  43     assert_op("Match", out_m, m, op)
  44
  45 # Checks the state of the CAM entry
  46 # Arguments:
  47 #   dut: The CamEntry being tested
  48 #   d (data): The expected data
  49 #   m (match): The expected match
  50 #   d_op (Operation): Operation for the data assertion (0 => ==), (1 => !=)
  51 #   m_op (Operation): Operation for the match assertion (0 => ==), (1 => !=)
  52
  53
  54 def check_all(dut, d, m, d_op, m_op):
  55     yield from check_data(dut, d, d_op)
  56     yield from check_match(dut, m, m_op)
  57
  58 # This tbench goes through the paces of testing the CamEntry module
  59 # It is done by writing and then reading various combinations of key/data pairs
  60 # and reading the results with varying keys to verify the resulting stored
  61 # data is correct.
  62
  63
  64 def tbench(dut):
  65     # Check write
  66     command = 2
  67     data = 1
  68     match = 0
  69     yield from set_cam_entry(dut, command, data)
  70     yield from check_all(dut, data, match, 0, 0)
  71
  72     # Check read miss
  73     command = 1
  74     data = 2
  75     match = 0
  76     yield from set_cam_entry(dut, command, data)
  77     yield from check_all(dut, data, match, 1, 0)
  78
  79     # Check read hit
  80     command = 1
  81     data = 1
  82     match = 1
  83     yield from set_cam_entry(dut, command, data)
  84     yield from check_all(dut, data, match, 0, 0)
  85
  86     # Check overwrite
  87     command = 2
  88     data = 5
  89     match = 0
  90     yield from set_cam_entry(dut, command, data)
  91     yield
  92     yield from check_all(dut, data, match, 0, 0)
  93
  94     # Check read hit
  95     command = 1
  96     data = 5
  97     match = 1
  98     yield from set_cam_entry(dut, command, data)
  99     yield from check_all(dut, data, match, 0, 0)
 100
 101     # Check reset
 102     command = 3
 103     data = 0
 104     match = 0
 105     yield from set_cam_entry(dut, command, data)
 106     yield from check_all(dut, data, match, 0, 0)
 107
 108     # Extra clock cycle for waveform
 109     yield
 110
 111
 112 def test_camentry():
 113     dut = CamEntry(4)
 114     run_simulation(dut, tbench(dut), vcd_name="Waveforms/test_cam_entry.vcd")
 115     print("CamEntry Unit Test Success")
 116
 117
 118 if __name__ == "__main__":
 119     test_camentry()