1 # this file has been generated by sv2nmigen
3 from nmigen
import Signal
, Module
, Const
, Cat
, Elaboratable
6 class axi4_r_buffer(Elaboratable
):
9 self
.axi4_aclk
= Signal() # input
10 self
.axi4_arstn
= Signal() # input
11 self
.s_axi4_rid
= Signal(AXI_ID_WIDTH
) # output
12 self
.s_axi4_rresp
= Signal(2) # output
13 self
.s_axi4_rdata
= Signal(AXI_DATA_WIDTH
) # output
14 self
.s_axi4_rlast
= Signal() # output
15 self
.s_axi4_rvalid
= Signal() # output
16 self
.s_axi4_ruser
= Signal(AXI_USER_WIDTH
) # output
17 self
.s_axi4_rready
= Signal() # input
18 self
.m_axi4_rid
= Signal(AXI_ID_WIDTH
) # input
19 self
.m_axi4_rresp
= Signal(2) # input
20 self
.m_axi4_rdata
= Signal(AXI_DATA_WIDTH
) # input
21 self
.m_axi4_rlast
= Signal() # input
22 self
.m_axi4_rvalid
= Signal() # input
23 self
.m_axi4_ruser
= Signal(AXI_USER_WIDTH
) # input
24 self
.m_axi4_rready
= Signal() # output
26 def elaborate(self
, platform
=None):
28 m
.d
.comb
+= self
.None.eq(self
.m_axi4_rresp
)
29 m
.d
.comb
+= self
.None.eq(self
.m_axi4_rlast
)
30 m
.d
.comb
+= self
.None.eq(self
.m_axi4_rid
)
31 m
.d
.comb
+= self
.None.eq(self
.m_axi4_rdata
)
32 m
.d
.comb
+= self
.None.eq(self
.m_axi4_ruser
)
33 m
.d
.comb
+= self
.s_axi4_rresp
.eq(self
.None)
34 m
.d
.comb
+= self
.s_axi4_rlast
.eq(self
.None)
35 m
.d
.comb
+= self
.s_axi4_rid
.eq(self
.None)
36 m
.d
.comb
+= self
.s_axi4_rdata
.eq(self
.None)
37 m
.d
.comb
+= self
.s_axi4_ruser
.eq(self
.None)
40 # // Copyright 2018 ETH Zurich and University of Bologna.
41 # // Copyright and related rights are licensed under the Solderpad Hardware
42 # // License, Version 0.51 (the "License"); you may not use this file except in
43 # // compliance with the License. You may obtain a copy of the License at
44 # // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
45 # // or agreed to in writing, software, hardware and materials distributed under
46 # // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
47 # // CONDITIONS OF ANY KIND, either express or implied. See the License for the
48 # // specific language governing permissions and limitations under the License.
50 # module axi4_r_buffer
52 # parameter AXI_DATA_WIDTH = 32,
53 # parameter AXI_ID_WIDTH = 4,
54 # parameter AXI_USER_WIDTH = 4
57 # input logic axi4_aclk,
58 # input logic axi4_arstn,
60 # output logic [AXI_ID_WIDTH-1:0] s_axi4_rid,
61 # output logic [1:0] s_axi4_rresp,
62 # output logic [AXI_DATA_WIDTH-1:0] s_axi4_rdata,
63 # output logic s_axi4_rlast,
64 # output logic s_axi4_rvalid,
65 # output logic [AXI_USER_WIDTH-1:0] s_axi4_ruser,
66 # input logic s_axi4_rready,
68 # input logic [AXI_ID_WIDTH-1:0] m_axi4_rid,
69 # input logic [1:0] m_axi4_rresp,
70 # input logic [AXI_DATA_WIDTH-1:0] m_axi4_rdata,
71 # input logic m_axi4_rlast,
72 # input logic m_axi4_rvalid,
73 # input logic [AXI_USER_WIDTH-1:0] m_axi4_ruser,
74 # output logic m_axi4_rready
77 # wire [AXI_DATA_WIDTH+AXI_ID_WIDTH+AXI_USER_WIDTH+3-1:0] data_in;
78 # wire [AXI_DATA_WIDTH+AXI_ID_WIDTH+AXI_USER_WIDTH+3-1:0] data_out;
80 # localparam ID_START = 3;
81 # localparam ID_END = AXI_ID_WIDTH-1 + ID_START;
82 # localparam DATA_START = ID_END + 1;
83 # localparam DATA_END = AXI_DATA_WIDTH-1 + DATA_START;
84 # localparam USER_START = DATA_END + 1;
85 # localparam USER_END = AXI_USER_WIDTH-1 + USER_START;
87 # assign data_in [1:0] = m_axi4_rresp;
88 # assign data_in [2] = m_axi4_rlast;
89 # assign data_in [ID_END:ID_START] = m_axi4_rid;
90 # assign data_in[DATA_END:DATA_START] = m_axi4_rdata;
91 # assign data_in[USER_END:USER_START] = m_axi4_ruser;
93 # assign s_axi4_rresp = data_out [1:0];
94 # assign s_axi4_rlast = data_out [2];
95 # assign s_axi4_rid = data_out [ID_END:ID_START];
96 # assign s_axi4_rdata = data_out[DATA_END:DATA_START];
97 # assign s_axi4_ruser = data_out[USER_END:USER_START];
101 # .DATA_WIDTH ( AXI_DATA_WIDTH+AXI_ID_WIDTH+AXI_USER_WIDTH+3 ),
102 # .BUFFER_DEPTH ( 4 )
106 # .clk ( axi4_aclk ),
107 # .rstn ( axi4_arstn ),
109 # .valid_out ( s_axi4_rvalid ),
110 # .data_out ( data_out ),
111 # .ready_in ( s_axi4_rready ),
113 # .valid_in ( m_axi4_rvalid ),
114 # .data_in ( data_in ),
115 # .ready_out ( m_axi4_rready )