unused_please_ignore_completely/iommu/axi_rab/axi4_w_sender.py

   1 # this file has been generated by sv2nmigen
   2
   3 from nmigen import Signal, Module, Const, Cat, Elaboratable
   4
   5
   6 class axi4_w_sender(Elaboratable):
   7
   8     def __init__(self):
   9         self.axi4_aclk = Signal()  # input
  10         self.axi4_arstn = Signal()  # input
  11         self.s_axi4_wdata = Signal()  # input
  12         self.s_axi4_wvalid = Signal()  # input
  13         self.s_axi4_wready = Signal()  # output
  14         self.s_axi4_wstrb = Signal()  # input
  15         self.s_axi4_wlast = Signal()  # input
  16         self.s_axi4_wuser = Signal()  # input
  17         self.m_axi4_wdata = Signal()  # output
  18         self.m_axi4_wvalid = Signal()  # output
  19         self.m_axi4_wready = Signal()  # input
  20         self.m_axi4_wstrb = Signal()  # output
  21         self.m_axi4_wlast = Signal()  # output
  22         self.m_axi4_wuser = Signal()  # output
  23
  24     def elaborate(self, platform=None):
  25         m = Module()
  26         m.d.comb += self.m_axi4_wdata.eq(self.s_axi4_wdata)
  27         m.d.comb += self.m_axi4_wstrb.eq(self.s_axi4_wstrb)
  28         m.d.comb += self.m_axi4_wlast.eq(self.s_axi4_wlast)
  29         m.d.comb += self.m_axi4_wuser.eq(self.s_axi4_wuser)
  30         m.d.comb += self.m_axi4_wvalid.eq(self.s_axi4_wvalid)
  31         m.d.comb += self.s_axi4_wready.eq(self.m_axi4_wready)
  32         return m
  33
  34 # // Copyright 2018 ETH Zurich and University of Bologna.
  35 # // Copyright and related rights are licensed under the Solderpad Hardware
  36 # // License, Version 0.51 (the "License"); you may not use this file except in
  37 # // compliance with the License.  You may obtain a copy of the License at
  38 # // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
  39 # // or agreed to in writing, software, hardware and materials distributed under
  40 # // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
  41 # // CONDITIONS OF ANY KIND, either express or implied. See the License for the
  42 # // specific language governing permissions and limitations under the License.
  43 #
  44 # module axi4_w_sender
  45 #  #(
  46 #    parameter AXI_DATA_WIDTH = 32,
  47 #    parameter AXI_USER_WIDTH = 2
  48 #  )
  49 #  (
  50 #    input                         axi4_aclk,
  51 #    input                         axi4_arstn,
  52 #
  53 #    input    [AXI_DATA_WIDTH-1:0] s_axi4_wdata,
  54 #    input                         s_axi4_wvalid,
  55 #    output                        s_axi4_wready,
  56 #    input  [AXI_DATA_WIDTH/8-1:0] s_axi4_wstrb,
  57 #    input                         s_axi4_wlast,
  58 #    input    [AXI_USER_WIDTH-1:0] s_axi4_wuser,
  59 #
  60 #    output   [AXI_DATA_WIDTH-1:0] m_axi4_wdata,
  61 #    output                        m_axi4_wvalid,
  62 #    input                         m_axi4_wready,
  63 #    output [AXI_DATA_WIDTH/8-1:0] m_axi4_wstrb,
  64 #    output                        m_axi4_wlast,
  65 #    output   [AXI_USER_WIDTH-1:0] m_axi4_wuser
  66 #  );
  67 #
  68 #  assign m_axi4_wdata  = s_axi4_wdata;
  69 #  assign m_axi4_wstrb  = s_axi4_wstrb;
  70 #  assign m_axi4_wlast  = s_axi4_wlast;
  71 #  assign m_axi4_wuser  = s_axi4_wuser;
  72 #
  73 #  assign m_axi4_wvalid = s_axi4_wvalid;
  74 #  assign s_axi4_wready = m_axi4_wready;
  75 #
  76 # endmodule
  77 #
  78 #