Allow the formal engine to perform a same-cycle result in the ALU
[soc.git] / unused_please_ignore_completely / iommu / axi_rab / test / test_slice_top.py
1 from nmigen.compat.sim import run_simulation
2 import sys
3 sys.path.append("../")
4 # sys.path.append("../../../TestUtil")
5 from slice_top import slice_top
6
7 def tbench(dut):
8 yield
9
10
11 if __name__ == "__main__":
12 dut = slice_top()
13 run_simulation(dut, tbench(dut), vcd_name="test_slice_top.vcd")
14 print("slice_top Unit Test Success")