"""regspec_decode functions for the relationship between regspecs and Decode2Execute1Type these functions encodes the understanding (relationship) between Regfiles, Computation Units, and the Power ISA Decoder (PowerDecoder2). based on the regspec, which contains the register file name and register name, return a tuple of: * how the decoder should determine whether the Function Unit needs access to a given Regport or not * which Regfile number on that port should be read to get that data * when it comes to writing: likewise, which Regfile num should be written Note that some of the port numbering encoding is *unary*. in the case of "Full Condition Register", it's a full 8-bit mask of read/write-enables. This actually matches directly with the XFX field in MTCR, and at some point that 8-bit mask from the instruction could actually be passed directly through to full_cr (TODO). For the INT and CR numbering, these are expressed in binary in the instruction (note however that XFX in MTCR is unary-masked!) XER is implicitly-encoded based on whether the operation has carry or overflow. FAST regfile is, again, implicitly encoded, back in PowerDecode2, based on the type of operation (see DecodeB for an example). The SPR regfile on the other hand is *binary*-encoded, and, furthermore, has to be "remapped". see https://libre-soc.org/3d_gpu/architecture/regfile/ section on regspecs """ from nmigen import Const from soc.regfile.regfiles import XERRegs, FastRegs from soc.decoder.power_enums import CryIn def regspec_decode_read(e, regfile, name): """regspec_decode_read """ if regfile == 'INT': # Int register numbering is *unary* encoded if name == 'ra': # RA return e.read_reg1.ok, 1<