"""simple core test, runs instructions from a TestMemory related bugs: * https://bugs.libre-soc.org/show_bug.cgi?id=363 """ from nmigen import Module, Signal, Cat, ClockSignal # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell # Also, check out the cxxsim nmigen branch, and latest yosys from git from nmutil.sim_tmp_alternative import Simulator, Settle from nmutil.formaltest import FHDLTestCase from nmutil.gtkw import write_gtkw from nmigen.cli import rtlil import unittest from soc.decoder.isa.caller import special_sprs from soc.decoder.isa.all import ISA from soc.decoder.power_enums import Function, XER_bits from soc.config.endian import bigendian from soc.decoder.power_decoder import create_pdecode from soc.decoder.power_decoder2 import PowerDecode2 from soc.simple.issuer import TestIssuerInternal from soc.experiment.compalu_multi import find_ok # hack from soc.config.test.test_loadstore import TestMemPspec from soc.simple.test.test_core import (setup_regs, check_regs, wait_for_busy_clear, wait_for_busy_hi) from soc.fu.compunits.test.test_compunit import (setup_test_memory, check_sim_memory) from soc.debug.dmi import DBGCore, DBGCtrl, DBGStat # test with ALU data and Logical data from soc.fu.alu.test.test_pipe_caller import ALUTestCase from soc.fu.div.test.test_pipe_caller import DivTestCases from soc.fu.logical.test.test_pipe_caller import LogicalTestCase from soc.fu.shift_rot.test.test_pipe_caller import ShiftRotTestCase from soc.fu.cr.test.test_pipe_caller import CRTestCase #from soc.fu.branch.test.test_pipe_caller import BranchTestCase #from soc.fu.spr.test.test_pipe_caller import SPRTestCase from soc.fu.ldst.test.test_pipe_caller import LDSTTestCase from soc.simulator.test_sim import (GeneralTestCases, AttnTestCase) #from soc.simulator.test_helloworld_sim import HelloTestCases def setup_i_memory(imem, startaddr, instructions): mem = imem print("insn before, init mem", mem.depth, mem.width, mem, len(instructions)) for i in range(mem.depth): yield mem._array[i].eq(0) yield Settle() startaddr //= 4 # instructions are 32-bit if mem.width == 32: mask = ((1 << 32)-1) for ins in instructions: if isinstance(ins, tuple): insn, code = ins else: insn, code = ins, '' insn = insn & 0xffffffff yield mem._array[startaddr].eq(insn) yield Settle() if insn != 0: print("instr: %06x 0x%x %s" % (4*startaddr, insn, code)) startaddr += 1 startaddr = startaddr & mask return # 64 bit mask = ((1 << 64)-1) for ins in instructions: if isinstance(ins, tuple): insn, code = ins else: insn, code = ins, '' insn = insn & 0xffffffff msbs = (startaddr >> 1) & mask val = yield mem._array[msbs] if insn != 0: print("before set", hex(4*startaddr), hex(msbs), hex(val), hex(insn)) lsb = 1 if (startaddr & 1) else 0 val = (val | (insn << (lsb*32))) val = val & mask yield mem._array[msbs].eq(val) yield Settle() if insn != 0: print("after set", hex(4*startaddr), hex(msbs), hex(val)) print("instr: %06x 0x%x %s %08x" % (4*startaddr, insn, code, val)) startaddr += 1 startaddr = startaddr & mask def set_dmi(dmi, addr, data): yield dmi.req_i.eq(1) yield dmi.addr_i.eq(addr) yield dmi.din.eq(data) yield dmi.we_i.eq(1) while True: ack = yield dmi.ack_o if ack: break yield yield yield dmi.req_i.eq(0) yield dmi.addr_i.eq(0) yield dmi.din.eq(0) yield dmi.we_i.eq(0) yield def get_dmi(dmi, addr): yield dmi.req_i.eq(1) yield dmi.addr_i.eq(addr) yield dmi.din.eq(0) yield dmi.we_i.eq(0) while True: ack = yield dmi.ack_o if ack: break yield yield # wait one data = yield dmi.dout # get data after ack valid for 1 cycle yield dmi.req_i.eq(0) yield dmi.addr_i.eq(0) yield dmi.we_i.eq(0) yield return data class TestRunner(FHDLTestCase): def __init__(self, tst_data, microwatt_mmu=False): super().__init__("run_all") self.test_data = tst_data self.microwatt_mmu = microwatt_mmu def run_all(self): m = Module() comb = m.d.comb pc_i = Signal(32) pspec = TestMemPspec(ldst_ifacetype='test_bare_wb', imem_ifacetype='test_bare_wb', addr_wid=48, mask_wid=8, imem_reg_wid=64, #wb_data_width=32, use_pll=False, nocore=False, xics=False, gpio=False, mmu=self.microwatt_mmu, reg_wid=64) m.submodules.issuer = issuer = TestIssuerInternal(pspec) imem = issuer.imem._get_memory() core = issuer.core dmi = issuer.dbg.dmi pdecode2 = issuer.pdecode2 l0 = core.l0 # copy of the decoder for simulator simdec = create_pdecode() simdec2 = PowerDecode2(simdec) m.submodules.simdec2 = simdec2 # pain in the neck # run core clock at same rate as test clock intclk = ClockSignal("coresync") comb += intclk.eq(ClockSignal()) comb += issuer.pc_i.data.eq(pc_i) # nmigen Simulation sim = Simulator(m) sim.add_clock(1e-6) def process(): # start in stopped yield from set_dmi(dmi, DBGCore.CTRL, 1<= len(instructions): print ("index over, send dmi stop") # stop at end yield from set_dmi(dmi, DBGCore.CTRL, 1<