adjust SVP64RM class to output more PowerDecoder-friendly csv augmentation

[soc.git] / .gitlab-ci.yml

diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 037653e935cc787ece3bb015f7604cc512564f65..de5914acbfaf70c4e53f41b01726c67565c44f20 100644 (file)
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -3,21 +3,25 @@ image: debian:10
 cache:
     paths:
         - ccache
+        - .cache/pip
+        - apt-cache
 
 variables:
+    PIP_CACHE_DIR: "$CI_PROJECT_DIR/.cache/pip"
     GIT_SUBMODULE_STRATEGY: recursive
 
 build:
     stage: build
     before_script:
-        - apt-get update
+        - mkdir -p apt-cache
+        - apt-get -o dir::cache::archives="$(pwd)/apt-cache" update
         - >-
-            apt-get -y install
+            apt-get -o dir::cache::archives="$(pwd)/apt-cache" -y install
             build-essential git python3-dev python3-pip
             python3-setuptools python3-wheel pkg-config tcl-dev
             libreadline-dev bison flex libffi-dev ccache python3-venv
             binutils-powerpc64-linux-gnu binutils-powerpc64le-linux-gnu
-            autoconf gperf libgmp-dev
+            autoconf gperf libgmp-dev libmpfr-dev libssl-dev
         - export PATH="/usr/lib/ccache:$PATH"
         - export CCACHE_BASEDIR="$PWD"
         - export CCACHE_DIR="$PWD/ccache"
@@ -63,6 +67,11 @@ build:
         - python setup.py develop
         - popd
 
+        - git clone --depth 1 git://git.libre-riscv.org/nmigen-soc.git nmigen-soc
+        - pushd nmigen-soc
+        - python setup.py develop
+        - popd
+
         - git clone --depth 1 git://git.libre-riscv.org/ieee754fpu.git ieee754fpu
         - pushd ieee754fpu
         - python setup.py develop