versa_ecp5 adds ability to build and load for ulx3s85f, fixes testgpio

[soc.git] / Makefile

diff --git a/Makefile b/Makefile
index 4f3abd1cb71cc0055abd7bf0af841e3da6ed8b01..9d7ae554eb38300625e81f7360b4a75107120e2f 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -18,9 +18,15 @@ develop:
        python3 src/soc/decoder/pseudo/pywriter.py
 
 run_sim: install
-       python3 src/soc/simple/issuer_verilog.py src/soc/litex/florent/libresoc/libresoc.v
+       python3 src/soc/simple/issuer_verilog.py src/soc/litex/florent/\
+       libresoc/libresoc.v
        python3 src/soc/litex/florent/sim.py --cpu=libresoc
 
+testgpio_run_sim:
+       python3 src/soc/simple/issuer_verilog.py src/soc/litex/florent/libresoc/\
+       libresoc.v --enable-testgpio
+       python3 src/soc/litex/florent/sim.py --cpu=libresoc --variant=standardjtagtestgpio
+
 test: install
        python3 setup.py test # could just run nosetest3...