add srcstep and correct PC-advancing during Sub-PC looping in ISACaller

[soc.git] / Makefile

diff --git a/Makefile b/Makefile
index 1df83c53d67950fc38b6145aded81d7aba02c61b..cd8c001dce74d25484ef460619d40e756170f96b 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -4,16 +4,31 @@ PYTHON3 ?= "python3"
 
 gitupdate:
        git submodule init
-       git submodule update --recursive
+       git submodule update --init --recursive --remote
 
-install:
-       python3 setup.py develop # yes, develop, not install
+mkpinmux:
+       ./mkpinmux.sh
+       cp pinmux/ls180/ls180_pins.py src/soc/debug
+       cp pinmux/ls180/ls180_pins.py src/soc/litex/florent/libresoc
+
+install: develop mkpinmux
+
+develop:
+       python3 setup.py develop --user # yes, develop, not install
        python3 src/soc/decoder/pseudo/pywriter.py
 
 run_sim: install
-       # TODO: get it to work
+       python3 src/soc/simple/issuer_verilog.py \
+                       src/soc/litex/florent/libresoc/libresoc.v
        python3 src/soc/litex/florent/sim.py --cpu=libresoc
 
+testgpio_run_sim:
+       python3 src/soc/simple/issuer_verilog.py \
+                       src/soc/litex/florent/libresoc/libresoc.v \
+                       --enable-testgpio
+       python3 src/soc/litex/florent/sim.py --cpu=libresoc \
+                       --variant=standardjtagtestgpio
+
 test: install
        python3 setup.py test # could just run nosetest3...