getting sim instruction decoder to reproduce asm instruction disassembly

[soc.git] / libreriscv

diff --git a/libreriscv b/libreriscv
index c732d3ea7f5f50c646f35a6de9ce629ee1450876..b4a37081cfd2985ffa7678597f2dd459c39c72ff 160000 (submodule)
--- a/libreriscv
+++ b/libreriscv
@@ -1 +1 @@
-Subproject commit c732d3ea7f5f50c646f35a6de9ce629ee1450876
+Subproject commit b4a37081cfd2985ffa7678597f2dd459c39c72ff