add srcstep and correct PC-advancing during Sub-PC looping in ISACaller

[soc.git] / setup.py

diff --git a/setup.py b/setup.py
index 246dd66bcfc5162eeb83d43375d20fa713e3fd6a..3a58066a8bb70077b035500e46d82b98acfbbbb9 100644 (file)
--- a/setup.py
+++ b/setup.py
@@ -11,30 +11,33 @@ version = '0.0.1'
 
 install_requires = [
     #    'sfpy',
-    'ieee754fpu',  # needs to be installed manually
+    'ieee754fpu',  # needs to be installed manually from git.libre-soc.org
     'pygdbmi',
+    'nmigen-soc',  # install manually from git.libre-soc.org
     'ply',  # needs to be installed manually
-    'astor',
+    'astor'
 ]
 
 test_requires = [
     'nose',
+    # install from https://salsa.debian.org/Kazan-team/power-instruction-analyzer
+    'power-instruction-analyzer'
 ]
 
 setup(
     name='soc',
     version=version,
-    description="A nmigen-based OpenPOWER Hybrid CPU / VPU / GPU",
+    description="A nmigen-based OpenPOWER multi-issue Hybrid CPU / VPU / GPU",
     long_description=README + '\n\n' + NEWS,
     classifiers=[
         "Topic :: Software Development :: Libraries",
         "License :: OSI Approved :: LGPLv3+",
         "Programming Language :: Python :: 3",
     ],
-    keywords='nmigen ieee754 libre-riscv soc',
+    keywords='nmigen ieee754 libre-soc soc',
     author='Luke Kenneth Casson Leighton',
-    author_email='lkcl@libre-riscv.org',
-    url='http://git.libre-riscv.org/?p=soc',
+    author_email='lkcl@libre-soc.org',
+    url='http://git.libre-soc.org/?p=soc',
     license='GPLv3+',
     packages=find_packages('src'),
     package_dir={'': 'src'},