add SVP64 CR EXTRA field-extension, from 3-bit to 7-bit (plus isvec)

[soc.git] / setup.py

diff --git a/setup.py b/setup.py
index dc3c71f533252f31a4fea345885631b7ffd4d6e1..3a58066a8bb70077b035500e46d82b98acfbbbb9 100644 (file)
--- a/setup.py
+++ b/setup.py
@@ -15,11 +15,13 @@ install_requires = [
     'pygdbmi',
     'nmigen-soc',  # install manually from git.libre-soc.org
     'ply',  # needs to be installed manually
-    'astor',
+    'astor'
 ]
 
 test_requires = [
     'nose',
+    # install from https://salsa.debian.org/Kazan-team/power-instruction-analyzer
+    'power-instruction-analyzer'
 ]
 
 setup(