add in 2 more ALUs, now 4x4 scoreboard

[soc.git] / src / scoreboard / group_picker.py

diff --git a/src/scoreboard/group_picker.py b/src/scoreboard/group_picker.py
index 333d5b1b8a6e2f6d00cfd71129fd5f06b76bb3a3..f02f88630e7080d6b3109c03d41a929f01605ab6 100644 (file)
--- a/src/scoreboard/group_picker.py
+++ b/src/scoreboard/group_picker.py
@@ -10,21 +10,22 @@ class PriorityPicker(Elaboratable):
         self.wid = wid
         # inputs
         self.i = Signal(wid, reset_less=True)
-        self.o = Signal(wid, reset_less=True) 
+        self.o = Signal(wid, reset_less=True)
 
     def elaborate(self, platform):
         m = Module()
 
         res = []
+        ni = Signal(self.wid, reset_less = True)
+        m.d.comb += ni.eq(~self.i)
         for i in range(0, self.wid):
             t = Signal(reset_less = True)
             res.append(t)
             if i == 0:
-                m.d.comb += t.eq(self.i[0])
+                m.d.comb += t.eq(self.i[i])
             else:
-                m.d.comb += t.eq((~res[-2]) & self.i[i])
-            res.append(t)
-        
+                m.d.comb += t.eq(~Cat(ni[i], *self.i[:i]).bool())
+
         # we like Cat(*xxx).  turn lists into concatenated bits
         m.d.comb += self.o.eq(Cat(*res))
 
@@ -33,7 +34,7 @@ class PriorityPicker(Elaboratable):
     def __iter__(self):
         yield self.i
         yield self.o
-                
+
     def ports(self):
         return list(self)
 
@@ -46,6 +47,7 @@ class GroupPicker(Elaboratable):
         # inputs
         self.readable_i = Signal(wid, reset_less=True) # readable in (top)
         self.writable_i = Signal(wid, reset_less=True) # writable in (top)
+        self.rd_rel_i = Signal(wid, reset_less=True)   # go read in (top)
         self.req_rel_i = Signal(wid, reset_less=True) # release request in (top)
 
         # outputs
@@ -62,7 +64,7 @@ class GroupPicker(Elaboratable):
         m.d.comb += wpick.i.eq(self.writable_i & self.req_rel_i)
         m.d.comb += self.go_wr_o.eq(wpick.o)
 
-        m.d.comb += rpick.i.eq(self.readable_i)
+        m.d.comb += rpick.i.eq(self.readable_i & self.rd_rel_i)
         m.d.comb += self.go_rd_o.eq(rpick.o)
 
         return m
@@ -73,7 +75,7 @@ class GroupPicker(Elaboratable):
         yield self.req_rel_i
         yield self.go_rd_o
         yield self.go_wr_o
-                
+
     def ports(self):
         return list(self)
 
@@ -91,9 +93,9 @@ def grp_pick_sim(dut):
     yield
     yield dut.issue_i.eq(0)
     yield
-    yield dut.go_rd_i.eq(1)
+    yield dut.rd_rel_i.eq(1)
     yield
-    yield dut.go_rd_i.eq(0)
+    yield dut.rd_rel_i.eq(0)
     yield
     yield dut.go_wr_i.eq(1)
     yield