Re-enable rlwinm test

[soc.git] / src / soc / alu / test / test_pipe_caller.py

diff --git a/src/soc/alu/test/test_pipe_caller.py b/src/soc/alu/test/test_pipe_caller.py
index d3ec23abe7336f1cde9934077624a1fa02f5e4bd..9d44730d07418f0c254c41f7be8605ce6f69c05e 100644 (file)
--- a/src/soc/alu/test/test_pipe_caller.py
+++ b/src/soc/alu/test/test_pipe_caller.py
@@ -178,7 +178,6 @@ class ALUTestCase(FHDLTestCase):
         with Program(lst) as program:
             sim = self.run_tst_program(program, initial_regs)
 
-    @unittest.skip("broken")
     def test_rlwinm(self):
         for i in range(10):
             mb = random.randint(0,31)
@@ -192,15 +191,13 @@ class ALUTestCase(FHDLTestCase):
 
     @unittest.skip("broken")
     def test_rlwimi(self):
-        lst = ["rlwinm 3, 1, 5, 20, 6",
-               "rlwimi 3, 1, 5, 20, 6"]
+        lst = ["rlwimi 3, 1, 5, 20, 6"]
         initial_regs = [0] * 32
-        initial_regs[1] = random.randint(0, (1<<64)-1)
-        initial_regs[3] = random.randint(0, (1<<64)-1)
+        initial_regs[1] = 0xdeadbeef
+        initial_regs[3] = 0x12345678
         with Program(lst) as program:
             sim = self.run_tst_program(program, initial_regs)
 
-    @unittest.skip("broken")
     def test_rlwnm(self):
         lst = ["rlwnm 3, 1, 2, 20, 6"]
         initial_regs = [0] * 32