self.clk_sel_i = Signal(2, reset_less=True) # PLL selection
self.clk_pll_o = Signal(reset_less=True) # output fake PLL clock
self.pll_18_o = Signal(reset_less=True) # 16-divide from PLL
- self.clk_lck_o = Signal(reset_less=True) # output fake PLL "lock"
+ self.pll_lck_o = Signal(reset_less=True) # output fake PLL "lock"
def elaborate(self, platform):
m = Module()
# just get something, stops yosys destroying (optimising) these out
m.d.comb += self.pll_18_o.eq(self.clk_24_i)
with m.If(self.clk_sel_i == Const(0, 2)):
- m.d.comb += self.clk_lck_o.eq(self.clk_24_i)
+ m.d.comb += self.pll_lck_o.eq(self.clk_24_i)
return m