reorder / reorganise reset signals slightly

[soc.git] / src / soc / clock / select.py

diff --git a/src/soc/clock/select.py b/src/soc/clock/select.py
index 7a2b3fc914126e0f229f4fb714207cfed059d405..5ca7ba9065fcc4f7e038e2c74375f7cc7e4fa6b3 100644 (file)
--- a/src/soc/clock/select.py
+++ b/src/soc/clock/select.py
@@ -14,10 +14,11 @@
   the CLK_24 is the default in case PLL is unstable
 """
 
-from nmigen import (Module, Array, Signal, Mux, Elaboratable, ClockSignal)
+from nmigen import (Module, Array, Signal, Mux, Elaboratable, ClockSignal,
+                    ResetSignal)
 from nmigen.cli import rtlil
 
-CLK_24 = 0b000
+CLK_24 = 0b000 # this is the default (clk_sel_i = 0 on reset)
 PLL6 = 0b001
 PLL4 = 0b010
 PLL3 = 0b011
@@ -44,7 +45,7 @@ class ClockSelect(Elaboratable):
         counter3 = Signal(2) # for divide-by-3
 
         # set up system, zero and one clocks
-        comb += clkgen[SYS_CLK].eq(self.clk_24_i) # 1st is external 24mhz
+        comb += clkgen[CLK_24].eq(self.clk_24_i) # 1st is external 24mhz
         comb += clkgen[ZERO].eq(0) # LOW (use with ONE for direct driving)
         comb += clkgen[ONE].eq(1) # HI
 
@@ -72,6 +73,21 @@ class ClockSelect(Elaboratable):
         return [self.clk_24_i, self.pll_48_o, self.clk_sel_i, self.core_clk_o]
 
 
+class DummyPLL(Elaboratable):
+    def __init__(self):
+        self.clk_24_i = Signal() # 24 mhz external incoming
+        self.clk_pll_o = Signal()  # output fake PLL clock
+
+    def elaborate(self, platform):
+        m = Module()
+        m.d.comb += self.clk_pll_o.eq(self.clk_24_i) # just pass through
+
+        return m
+
+    def ports(self):
+        return [self.clk_24_i, self.clk_pll_o]
+
+
 if __name__ == '__main__':
     dut = ClockSelect()