radix: reading first page table entry

[soc.git] / src / soc / consts.py

diff --git a/src/soc/consts.py b/src/soc/consts.py
index 108a730d5db8d47d7c7267104af3167b4a9efc24..8d537cd891aca9a1b67cbce5aef410debeef3a63 100644 (file)
--- a/src/soc/consts.py
+++ b/src/soc/consts.py
@@ -80,32 +80,6 @@ def field(r, msb0_start, msb0_end=None, field_width=64):
         return r[field_slice(msb0_start, msb0_end, field_width)]
 
 
-def sel(r, sel_bits, field_width=None):
-    """Forms a subfield from a selection of bits of the signal `r`
-    ("register").
-
-    :param r: signal containing the field from which to select the subfield
-    :param sel_bits: bit indices of the subfield, in "MSB 0" convention,
-                     from most significant to least significant. Note that
-                     the indices are allowed to be non-contiguous and
-                     out-of-order.
-    :param field_width: field width. If absent, use the signal `r` own width.
-    """
-    # find the MSB index in LSB0 numbering
-    if field_width is None:
-        msb = len(r) - 1
-    else:
-        msb = field_width - 1
-    # extract the selected bits
-    sig_list = []
-    for idx in sel_bits:
-        sig_list.append(r[msb - idx])
-    # place the LSB at the front of the list,
-    # since, in nMigen, Cat starts from the LSB
-    sig_list.reverse()
-    return Cat(*sig_list)
-
-
 # Listed in V3.0B Book III Chap 4.2.1
 # MSR bit numbers, *bigendian* order (PowerISA format)
 # use this in the simulator
@@ -218,15 +192,24 @@ class EXTRA3:
     IDX0 = [0, 1, 2]
     IDX1 = [3, 4, 5]
     IDX2 = [6, 7, 8]
+    MASK = [6, 7, 8]
 
 
 EXTRA3_SIZE = 9
 
 
+# SVP64 ReMapped Field (from v3.1 EXT001 Prefix)
 class SVP64P:
     OPC = range(0, 6)
     SVP64_7_9 = [7, 9]
     RM = [6, 8] + list(range(10, 32))
 
-
+# 24 bits in RM
 SVP64P_SIZE = 24
+
+
+# CR SVP64 offsets
+class SVP64CROffs:
+    CR0 = 0    # TODO: increase when CRs are expanded to 128
+    CR1 = 1    # TODO: increase when CRs are expanded to 128
+