radix: reading first page table entry

[soc.git] / src / soc / consts.py

diff --git a/src/soc/consts.py b/src/soc/consts.py
index 25ce875883082f697776e52fade4b4989fa75dcd..8d537cd891aca9a1b67cbce5aef410debeef3a63 100644 (file)
--- a/src/soc/consts.py
+++ b/src/soc/consts.py
@@ -1,9 +1,12 @@
 # sigh create little-ended versions of bitfield flags
-def botchify(bekls, lekls):
+from nmigen import Cat
+
+
+def botchify(bekls, lekls, msb=63):
     for attr in dir(bekls):
         if attr[0] == '_':
             continue
-        setattr(lekls, attr, 63-getattr(bekls, attr))
+        setattr(lekls, attr, msb-getattr(bekls, attr))
 
 
 # Can't think of a better place to put these functions.
@@ -74,7 +77,7 @@ def field(r, msb0_start, msb0_end=None, field_width=64):
     if msb0_end is None:
         return r[(field_width - 1) - msb0_start]
     else:
-        return r[field_slice(msb0_start, msb0_end)]
+        return r[field_slice(msb0_start, msb0_end, field_width)]
 
 
 # Listed in V3.0B Book III Chap 4.2.1
@@ -149,3 +152,64 @@ class TT:
     ILLEG = 1<<7 # currently the max
     # TODO: support for TM_BAD_THING (not included yet in trap main_stage.py)
     size = 8 # MUST update this to contain the full number of Trap Types
+
+
+# EXTRA3 3-bit subfield (spec)
+class SPECb:
+    VEC = 0  # 1 for vector, 0 for scalar
+    MSB = 1  # augmented register number, MSB
+    LSB = 2  # augmented register number, LSB
+
+
+SPEC_SIZE = 3
+SPEC_AUG_SIZE = 2  # augmented subfield size (MSB+LSB above)
+class SPEC:
+    pass
+botchify(SPECb, SPEC, SPEC_SIZE-1)
+
+
+# EXTRA field, with EXTRA2 subfield encoding
+class EXTRA2b:
+    IDX0_VEC = 0
+    IDX0_MSB = 1
+    IDX1_VEC = 2
+    IDX1_MSB = 3
+    IDX2_VEC = 4
+    IDX2_MSB = 5
+    IDX3_VEC = 6
+    IDX3_MSB = 7
+    RESERVED = 8
+
+
+EXTRA2_SIZE = 9
+class EXTRA2:
+    pass
+botchify(EXTRA2b, EXTRA2, EXTRA2_SIZE-1)
+
+
+# EXTRA field, with EXTRA3 subfield encoding
+class EXTRA3:
+    IDX0 = [0, 1, 2]
+    IDX1 = [3, 4, 5]
+    IDX2 = [6, 7, 8]
+    MASK = [6, 7, 8]
+
+
+EXTRA3_SIZE = 9
+
+
+# SVP64 ReMapped Field (from v3.1 EXT001 Prefix)
+class SVP64P:
+    OPC = range(0, 6)
+    SVP64_7_9 = [7, 9]
+    RM = [6, 8] + list(range(10, 32))
+
+# 24 bits in RM
+SVP64P_SIZE = 24
+
+
+# CR SVP64 offsets
+class SVP64CROffs:
+    CR0 = 0    # TODO: increase when CRs are expanded to 128
+    CR1 = 1    # TODO: increase when CRs are expanded to 128
+