if asmcode:
self.asmcode = Signal(8, reset_less=True) # only for simulator
- self.write_reg = Data(5, name="rego")
- self.write_ea = Data(5, name="ea") # for LD/ST in update mode
- self.read_reg1 = Data(5, name="reg1")
- self.read_reg2 = Data(5, name="reg2")
- self.read_reg3 = Data(5, name="reg3")
+ self.write_reg = Data(7, name="rego")
+ self.write_ea = Data(7, name="ea") # for LD/ST in update mode
+ self.read_reg1 = Data(7, name="reg1")
+ self.read_reg2 = Data(7, name="reg2")
+ self.read_reg3 = Data(7, name="reg3")
self.write_spr = Data(SPR, name="spro")
self.read_spr1 = Data(SPR, name="spr1")
#self.read_spr2 = Data(SPR, name="spr2") # only one needed
self.write_fast1 = Data(3, name="fasto1")
self.write_fast2 = Data(3, name="fasto2")
- self.read_cr1 = Data(3, name="cr_in1")
- self.read_cr2 = Data(3, name="cr_in2")
- self.read_cr3 = Data(3, name="cr_in2")
- self.write_cr = Data(3, name="cr_out")
+ self.read_cr1 = Data(7, name="cr_in1")
+ self.read_cr2 = Data(7, name="cr_in2")
+ self.read_cr3 = Data(7, name="cr_in2")
+ self.write_cr = Data(7, name="cr_out")
# decode operand data
print ("decode2execute init", name, opkls, do)