rename invert_a to invert_in because logical inverts RB

[soc.git] / src / soc / decoder / formal / proof_decoder2.py

diff --git a/src/soc/decoder/formal/proof_decoder2.py b/src/soc/decoder/formal/proof_decoder2.py
index 195044738bd693777a00b025e65e16d6d356eaf2..b7ac61f708ff3bfab70150e7a422b9366d710b8e 100644 (file)
--- a/src/soc/decoder/formal/proof_decoder2.py
+++ b/src/soc/decoder/formal/proof_decoder2.py
@@ -182,7 +182,7 @@ class Driver(Elaboratable):
         pdecode2 = m.submodules.pdecode2
         dec = pdecode2.dec
         e = pdecode2.e
-        comb += Assert(e.invert_a == dec.op.inv_a)
+        comb += Assert(e.invert_in == dec.op.inv_a)
         comb += Assert(e.invert_out == dec.op.inv_out)
         comb += Assert(e.input_carry == dec.op.cry_in)
         comb += Assert(e.output_carry == dec.op.cry_out)