End VL loop as soon as either src/dst step reaches VL

[soc.git] / src / soc / decoder / isa / caller.py

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index 95dc0f47c54934a6c60ab84256eb27345b0be689..2c784b3c1f5cc31bcdd03e02747e5edcd04bc567 100644 (file)
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -979,7 +979,7 @@ class ISACaller:
 
             # check if end reached (we let srcstep overrun, above)
             # nothing needs doing (TODO zeroing): just do next instruction
-            if srcstep == vl:
+            if srcstep == vl or dststep == vl:
                 self.svp64_reset_loop()
                 self.update_pc_next()
                 return
@@ -1145,7 +1145,7 @@ class ISACaller:
                 svp64_is_vector = (no_out_vec or no_in_vec)
             else:
                 svp64_is_vector = no_out_vec
-            if svp64_is_vector and srcstep != vl-1:
+            if svp64_is_vector and srcstep != vl-1 and dststep != vl-1:
                 self.svstate.srcstep += SelectableInt(1, 7)
                 self.svstate.dststep += SelectableInt(1, 7)
                 self.pc.NIA.value = self.pc.CIA.value