test SVP64 major opcode, start checking if it is EXT001 soon

[soc.git] / src / soc / decoder / isa / caller.py

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index bd516ebb6d0d985bdb136ec12134f0908d7599aa..38a439f087d2827280c1ea9ac3669047448f2d20 100644 (file)
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -13,6 +13,7 @@ related bugs:
 * https://bugs.libre-soc.org/show_bug.cgi?id=424
 """
 
+from nmigen.back.pysim import Settle
 from functools import wraps
 from copy import copy
 from soc.decoder.orderedset import OrderedSet
@@ -218,7 +219,7 @@ class SVP64State:
     def __init__(self, init=0):
         self.spr = SelectableInt(init, 32)
         # fields of SVSTATE, see https://libre-soc.org/openpower/sv/sprs/
-        self.maxvl = FieldSelectableInt(self.spr, tuple(range(0,7))
+        self.maxvl = FieldSelectableInt(self.spr, tuple(range(0,7)))
         self.vl = FieldSelectableInt(self.spr, tuple(range(7,14)))
         self.srcstep = FieldSelectableInt(self.spr, tuple(range(14,21)))
         self.dststep = FieldSelectableInt(self.spr, tuple(range(21,28)))
@@ -241,14 +242,14 @@ class SVP64RMFields:
 
 
 # SVP64 Prefix fields: see https://libre-soc.org/openpower/sv/svp64/
-class SPP64PrefixFields:
+class SVP64PrefixFields:
     def __init__(self):
         self.insn = SelectableInt(0, 32)
         # 6 bit major opcode EXT001, 2 bits "identifying" (7, 9), 24 SV ReMap
         self.major = FieldSelectableInt(self.insn, tuple(range(0,6)))
-        self.pid = FieldSelectableInt(self.insn, (7, 9) # must be 0b11
+        self.pid = FieldSelectableInt(self.insn, (7, 9)) # must be 0b11
         rmfields = [6, 8] + list(range(10,32)) # SVP64 24-bit RM
-        self.rm = FieldSelectableInt(self.spr, rmfields)
+        self.rm = FieldSelectableInt(self.insn, rmfields)
 
 
 class SPR(dict):
@@ -358,7 +359,7 @@ class ISACaller:
         self.mem = Mem(row_bytes=8, initial_mem=initial_mem)
         self.imem = Mem(row_bytes=4, initial_mem=initial_insns)
         self.pc = PC()
-        self.svstate = SVSTATE(initial_svstate)
+        self.svstate = SVP64State(initial_svstate)
         self.spr = SPR(decoder2, initial_sprs)
         self.msr = SelectableInt(initial_msr, 64)  # underlying reg
 
@@ -607,6 +608,14 @@ class ISACaller:
         yield self.dec2.state.msr.eq(self.msr.value)
         yield self.dec2.state.pc.eq(pc)
 
+        # SVP64.  first, check if the opcode is EXT001
+        yield Settle()
+        opcode = yield self.dec2.dec.opcode_in
+        pfx = SVP64PrefixFields()
+        pfx.insn.value = opcode
+        major = pfx.major.asint(msb0=True) # MSB0 inversion
+        print ("prefix test: opcode:", major, bin(major))
+
     def execute_one(self):
         """execute one instruction
         """